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公开(公告)号:US3832769A
公开(公告)日:1974-09-03
申请号:US14698471
申请日:1971-05-26
Applicant: MINNESOTA MINING & MFG
Inventor: OLYPHANT M , ROHLOFF R
IPC: H01L21/60 , H01L23/495 , H01L23/498 , H01L23/538 , H01L49/02 , H05K1/00 , H05K1/11 , H05K3/40 , H05K3/42 , H05K3/32 , H05K3/36
CPC classification number: H05K1/113 , H01L23/49572 , H01L23/4985 , H01L23/5384 , H01L24/81 , H01L49/02 , H01L2224/16237 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H05K1/0393 , H05K3/4038 , H05K3/423 , H05K2201/0305 , H05K2201/0394 , H05K2201/09472 , H05K2201/09563 , H05K2201/10674 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165 , H01L2924/00
Abstract: A method for mounting semiconductor chips to printed circuitry via conductive columns which extend through the dielectric substrate and electrically communicate with a predetermined pattern of conductive leads on the opposite surface of the substrate. Printed circuitry useful for practicing the method is also provided.
Abstract translation: 一种通过导电柱将半导体芯片安装到印刷电路上的方法,所述导电柱延伸穿过电介质基片并与衬底的相对表面上的预定图案的导电引线电连通。 还提供了用于实施该方法的印刷电路。
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公开(公告)号:US3778530A
公开(公告)日:1973-12-11
申请号:US3778530D
申请日:1972-07-05
Applicant: REIMANN W
Inventor: REIMANN W
CPC classification number: H05K3/3421 , H05K1/111 , H05K3/062 , H05K3/064 , H05K3/108 , H05K3/243 , H05K7/1023 , H05K2201/0305 , H05K2201/0338 , H05K2201/09745 , H05K2201/10689 , H05K2203/0361 , H05K2203/0384 , H05K2203/048 , H05K2203/058 , H05K2203/167 , Y02P70/611 , Y02P70/613
Abstract: A printed circuit board for mounting integrated circuit and resistor network packages commonly referred to as flatpack components and a process for fabricating the circuit board. The printed circuit board has a conductive pattern of electrical connection pads for connecting to electrical leads from flatpack components and electrical conductors for connecting the pads to circuitry external to the board. A channel for receiving and aligning each electrical lead from a flatpack component is formed by printed circuit techniques. The surface layer of each channel is formed of solder which simplifies the process of electrically connecting flatpack leads and reduces errors occuring in the soldering process.
Abstract translation: 用于安装通常称为扁平封装部件的集成电路和电阻器网络封装的印刷电路板以及用于制造电路板的工艺。 印刷电路板具有电连接焊盘的导电图案,用于连接到来自扁平封装部件和电导体的电引线,用于将焊盘连接到板外部的电路。 用于通过印刷电路技术形成用于从扁平封装部件接收和对准每个电引线的通道。 每个通道的表面层由焊料形成,这简化了电连接扁平封装引线的过程,并减少了焊接过程中发生的错误。
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123.Process for forming interconnections in a multilayer circuit board 失效
Title translation: 在多层电路板中形成互连的过程公开(公告)号:US3464855A
公开(公告)日:1969-09-02
申请号:US3464855D
申请日:1966-09-06
Applicant: NORTH AMERICAN ROCKWELL
Inventor: SHAHEEN JOSEPH M , QUINTANA LEO J
IPC: C25D5/02 , H05K3/18 , H05K3/24 , H05K3/34 , H05K3/38 , H05K3/40 , H05K3/42 , H05K3/46 , B44D1/18 , H01B1/00
CPC classification number: C25D5/02 , H05K3/181 , H05K3/243 , H05K3/3463 , H05K3/386 , H05K3/4038 , H05K3/423 , H05K3/4647 , H05K2201/0305 , H05K2201/0355 , H05K2201/0394 , H05K2203/0542 , H05K2203/063 , H05K2203/0733
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124.
公开(公告)号:US3335489A
公开(公告)日:1967-08-15
申请号:US22580462
申请日:1962-09-24
Applicant: NORTH AMERICAN AVIATION INC
Inventor: GRANT WILLIAM E
CPC classification number: H05K3/4038 , C22C5/00 , C22C28/00 , H01R12/526 , H05K3/002 , H05K3/3463 , H05K2201/0305 , H05K2201/0394 , H05K2203/0554 , H05K2203/1184 , Y10T29/49165 , Y10T29/49993
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公开(公告)号:US3318993A
公开(公告)日:1967-05-09
申请号:US29428863
申请日:1963-07-11
Applicant: RCA CORP
Inventor: BEELITZ HOWARD R
IPC: G11C15/02 , G11C15/04 , G11C17/00 , G11C17/02 , G11C17/04 , G11C17/06 , H01C1/14 , H01C7/00 , H05K1/11 , H05K1/16 , H05K3/34 , H05K3/40 , H05K3/46
CPC classification number: H05K3/4617 , G11C15/02 , G11C15/04 , G11C17/00 , G11C17/02 , G11C17/04 , G11C17/06 , H01C1/14 , H01C7/00 , H05K1/115 , H05K1/16 , H05K1/167 , H05K3/3463 , H05K3/4038 , H05K3/4611 , H05K2201/0305 , H05K2201/096 , H05K2201/09845
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126.Electrical isolation means for components on a printed circuit board 失效
Title translation: 用于印刷电路板上组件的电气隔离装置公开(公告)号:US3296360A
公开(公告)日:1967-01-03
申请号:US42316665
申请日:1965-01-04
Applicant: GEN ELECTRIC
Inventor: FALER PAUL E
CPC classification number: H05K1/0266 , H05K1/0293 , H05K3/043 , H05K3/306 , H05K3/3452 , H05K3/3457 , H05K2201/0305 , H05K2201/09781 , H05K2201/09936 , H05K2201/10166 , H05K2203/0195 , H05K2203/044 , H05K2203/1115 , H05K2203/173 , H05K2203/175
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127.
公开(公告)号:US3250848A
公开(公告)日:1966-05-10
申请号:US30813963
申请日:1963-09-11
Applicant: RCA CORP
Inventor: BEELITZ HOWARD R , SCHNITZLER HANS F
CPC classification number: H05K3/4038 , H05K1/0287 , H05K1/0292 , H05K1/0293 , H05K1/0298 , H05K1/16 , H05K3/429 , H05K3/4611 , H05K2201/0305 , H05K2201/09454 , H05K2201/096 , H05K2201/09845 , H05K2201/09945 , H05K2203/063 , H05K2203/173 , H05K2203/175
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公开(公告)号:US3228093A
公开(公告)日:1966-01-11
申请号:US17118162
申请日:1962-02-05
Applicant: SCHJELDAHL CO G T
Inventor: BRATTON FRANCIS H
CPC classification number: H05K3/002 , H05K3/3468 , H05K3/363 , H05K3/4038 , H05K3/4092 , H05K3/4611 , H05K2201/0145 , H05K2201/0166 , H05K2201/0305 , H05K2201/0394 , H05K2201/0397 , H05K2201/041 , H05K2201/09563 , H05K2201/10477 , H05K2203/0789 , Y10T29/49155
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公开(公告)号:US3184830A
公开(公告)日:1965-05-25
申请号:US12859661
申请日:1961-08-01
Applicant: LANE WELDON V , MALECKI EDMUND E
Inventor: LANE WELDON V , MALECKI EDMUND E
CPC classification number: H05K3/3447 , H01R12/716 , H05K3/3468 , H05K3/4038 , H05K3/4046 , H05K3/4611 , H05K2201/0305 , H05K2201/096 , H05K2201/09845 , H05K2201/10189 , H05K2201/10303 , H05K2201/10939 , H05K2203/044 , H05K2203/045 , Y10T29/49149
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130.
公开(公告)号:US20240292514A1
公开(公告)日:2024-08-29
申请号:US18572369
申请日:2022-06-30
Applicant: Lisa Dräxlmaier GmbH
Inventor: Andreas Brinkmann
IPC: H05K1/02 , B23K1/00 , B23K101/42 , H05K1/18 , H05K3/34
CPC classification number: H05K1/0204 , B23K1/0016 , H05K1/0209 , H05K3/3421 , H05K3/3452 , H05K3/3485 , B23K2101/42 , H05K1/181 , H05K2201/0305 , H05K2201/0989 , H05K2201/09909 , H05K2201/10689 , H05K2203/0557 , H05K2203/1178
Abstract: The present disclosure relates to a method for the process-reliable soldering of a chip package onto a printed circuit board for the process-reliable soldering of a chip package. The printed circuit board has a metallic cooling surface, a plurality of metallic contact surfaces surrounding the cooling surface, and, on a side opposite the cooling surface, a rear metallic mating surface, the mating surface being connected to the cooling surface by open vias, and lanes of solder resist being arranged on the cooling surface, which lanes both divide the cooling surface into a plurality of partial surfaces and enclose the vias.
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