公开(公告)号：US20040016569A1

公开(公告)日：2004-01-29

申请号：US10205725

申请日：2002-07-26

Inventor： Jason A. Mix ,  Yun Ling ,  Alok Tripathi ,  Kent E. Mallory

IPC: H05K001/11

CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09309

Abstract: A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.

Abstract translation: 公开了同时降低多层附加卡的高频插入损耗和串扰的技术。 该技术基于选择性地去除边缘手指下方的地面和电源平面。 电源和接地层的这种选择性去除消除了边缘手指处的过剩电容，降低了高频下的插入损耗，同时保持与相关连接器的阻抗匹配。 同时，剩余的金属接地/电源平面提供电磁屏蔽，从而减少差分对之间的串扰。 对于高速模拟和数字应用，可以获得具有最小插入损耗和串扰的连接器的最佳性能。

公开(公告)号：US06665927B1

公开(公告)日：2003-12-23

申请号：US09474662

申请日：1999-12-29

Applicant: Keith E. Dow ,  Russell N. Shryock

Inventor： Keith E. Dow ,  Russell N. Shryock

IPC: H01R4300

CPC classification number: H05K1/0216 ,  H05K1/0225 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09663 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: A method for decreasing resonance in a printed circuit board (PCB) uses cuts in a ground plane to slow a signal passing through the ground plane. Cuts in the ground plane may be used alone or in conjunction with the lengthening of signal traces. Slowing the signal passing through the ground plane enables a mismatch between the signal transit time of the ground plane and a signal oscillation period of the circuit board to be obtained. The mismatch results in decreased resonance.

Abstract translation: 一种降低印刷电路板（PCB）谐振的方法使用接地平面中的切口来减慢通过接地平面的信号。 接地平面上的切割可以单独使用或与信号迹线延长一起使用。 降低通过接地层的信号能够使接地层的信号传播时间与要获得的电路板的信号振荡周期之间不匹配。 不匹配导致共振减少。

公开(公告)号：US20030218871A1

公开(公告)日：2003-11-27

申请号：US10445000

申请日：2003-05-27

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H01L021/00

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board having a high level of reliability in terms of electric connection against temperature changes caused by the actual operation of electronic equipment, a manufacturing process, a substrate for multilayer circuitry, and an electronic apparatus. The multilayer circuit board comprises a laminate of at least one insulating layer and at least one wiring layer, wherein the wiring layer is formed by a composite member comprising a first metal layer and a second metal layer formed on one or both sides of the first metal layer, the first metal layer having a smaller coefficient of thermal expansion than the second metal layer, the second metal layer having a higher electric conductivity than the first metal layer, wherein the insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer, the circuit board further comprising a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole, wherein the layer-to-layer interconnection portion in the blind via-hole is formed in such a manner as to be in contact with the surface of the second metal layer.

Abstract translation: 一种多层电路板，其具有与由电子设备的实际操作，制造工艺，多层电路的基板和电子设备引起的温度变化的电连接方面的高可靠性。 所述多层电路板包括至少一层绝缘层和至少一层布线层的叠层体，其中所述布线层由复合构件形成，所述复合构件包括形成在所述第一金属的一侧或两侧上的第一金属层和第二金属层 所述第一金属层具有比所述第二金属层更小的热膨胀系数，所述第二金属层具有比所述第一金属层更高的导电性，其中所述绝缘层具有盲孔，所述盲通孔具有由 第二金属层的表面，电路板还包括在绝缘层的表面和盲孔中的层间互连部分，其中盲通孔中的层间互连部分 形成为与第二金属层的表面接触的方式。

公开(公告)号：US20030214860A1

公开(公告)日：2003-11-20

申请号：US10393217

申请日：2003-03-19

Applicant: Finisar Corporation

Inventor： Ronald A. Greenlaw

IPC: G11C007/00

CPC classification number: H05K1/025 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/0243 ,  H05K1/0253 ,  H05K1/189 ,  H05K3/3447 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/10121 ,  H01L2924/00

Abstract: The present invention is an optoelectronic device including a circuit board with a plurality of signal traces, a first ground plane, and a second ground plane. The impedance of a signal trace is determined by which of the first ground plane and the second ground plane is closest to the signal trace. The area of the first ground plane coincident with a first signal trace is left intact in order to set the impedance of the first signal trace, by reference to the first ground plane. The area of the first ground plane coincident with a second signal trace is removed in order to set the impedance of the second signal trace, by reference to the second ground plane.

Abstract translation: 本发明是一种光电器件，其包括具有多个信号迹线的电路板，第一接地平面和第二接地平面。 信号迹线的阻抗由第一接地平面和第二接地平面中的哪一个最靠近信号迹线确定。 与第一信号迹线重合的第一接地层的面积保持不变，以便参照第一接地层设置第一信号迹线的阻抗。 去除与第二信号迹线重合的第一接地面的区域，以便通过参考第二接地平面设置第二信号迹线的阻抗。

公开(公告)号：US20030151905A1

公开(公告)日：2003-08-14

申请号：US10073701

申请日：2002-02-11

Applicant: ADC DSL Systems, Inc.

Inventor： Gary Gottlieb

IPC: H05K007/06

CPC classification number: H05K1/116 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A substrate having a conductive plane and a via passing through the conductive plane is provided. The conductive plane contacts the via to electrically interconnect the via and the conductive plane. A gap in the conductive plane separates a surface of the via from the conductive plane to provide an uninterrupted path for electrical current flowing substantially on the surface of the via.

Abstract translation: 提供具有导电平面和穿过导电平面的通孔的基板。 导电平面与通孔接触以使通孔和导电平面电互连。 导电平面中的间隙将通孔的表面与导电平面分开，以提供基本上在通孔表面上流动的电流的不间断路径。

公开(公告)号：US20030136580A1

公开(公告)日：2003-07-24

申请号：US10053810

申请日：2002-01-18

Inventor： Juan Chen ,  Adam J. Norman ,  Ponniah Ilavarasan

IPC: H05K001/11

CPC classification number: H05K1/0234 ,  H05K1/0227 ,  H05K1/095 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.

Abstract translation: 描述了一种降低电磁干扰并提高具有平面分割的印刷电路板中的信号质量的方法。 描述了使用有损插槽填充。 有损填充应用于平面分裂上方并挤压入槽中。 有损耗的材料有助于减少天线谐振。

公开(公告)号：US06590782B2

公开(公告)日：2003-07-08

申请号：US09825163

申请日：2001-04-03

Applicant: Gregory J. Fritz ,  Alejandra Anderson ,  Robin Berg ,  Todd Husom ,  Eric Sit

Inventor： Gregory J. Fritz ,  Alejandra Anderson ,  Robin Berg ,  Todd Husom ,  Eric Sit

IPC: H05K700

CPC classification number: H05K7/1425 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q1/155 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K7/186 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

公开(公告)号：US06583677B2

公开(公告)日：2003-06-24

申请号：US09974791

申请日：2001-10-12

Applicant: Jun Shintani ,  Terukazu Otsuki

Inventor： Jun Shintani ,  Terukazu Otsuki

IPC: H03L700

CPC classification number: H05K1/165 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1847 ,  H05K1/0237 ,  H05K3/0035 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2203/107 ,  H05K2203/171

Abstract: An oscillator including a circuit board having a dielectric layer therein; an oscillator circuit comprising its components and an inductor element, the components being mounted on a front surface of the circuit board and at least a part of the inductor element being internally disposed in the dielectric layer; and a back conductor provided on a back surface of the circuit board; wherein the back conductor has two or more slits or pinholes through which a laser beam is passed for partially cutting the dielectric layer together with the internally disposed inductor element at plural sites for adjustment of an oscillation characteristic.

公开(公告)号：US20030112710A1

公开(公告)日：2003-06-19

申请号：US10026059

申请日：2001-12-18

Inventor： John C. Eidson ,  Stanley P. Woods ,  Hans Sitte

IPC: G06F001/04 ,  G04F005/00

CPC classification number: G04F5/063 ,  G06F1/20 ,  H05K1/0201 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10371 ,  H05K2201/2036 ,  H05K2203/165 ,  H05K2203/304

Abstract: A variety of techniques for low cost reduction of thermal drift in electronic components. These techniques include structures for increasing the thermal mass of an electronic component and for insulating an electronic component from thermal drift caused by air flow as well as structures for thermally isolating an electronic component from heat flow on a circuit board.

Abstract translation: 各种低成本降低电子部件热漂移的技术。 这些技术包括用于增加电子部件的热质量并使电子部件与由空气流引起的热漂移绝缘的结构以及用于将电子部件与电路板上的热流隔离的结构。

公开(公告)号：US20030107056A1

公开(公告)日：2003-06-12

申请号：US10013326

申请日：2001-12-08

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： Tsun-Kit Chin ,  William Landucci

IPC: H01L027/10

CPC classification number: H05K1/025 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/162 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09781 ,  H01L2924/00

Abstract: To significantly reduce parasitic capacitance of component's landing pad, the present invention forms patterned holes in reference potential layers below the pad, thus effectively increasing the dielectric distance between the pad and the reference potential planes below the pad, raising the characteristic impedance of the pad above that of the trace connected to the pad. A controlled amount of parasitic capacitance is re-introduced to the pad by forming at least one grounded metal plate adjacent to the pad, bringing the characteristic impedance of the pad to substantially match that of the trace. The distance of the metal plates from the pad, and the configuration of the patterned holes are predetermined to substantially match the pad's impedance with that of the trace.

Abstract translation: 为了显着降低部件的着陆焊盘的寄生电容，本发明在焊盘下方的参考电位层中形成图案化的孔，从而有效地增加焊盘与焊盘之下的参考电位面之间的介电距离，从而提高焊盘上方的特性阻抗 痕迹连接到垫。 通过形成与焊盘相邻的至少一个接地金属板，将受控量的寄生电容重新引入焊盘，使焊盘的特性阻抗基本上与迹线的阻抗一致。 金属板与焊盘的距离以及图案化孔的构型被预先确定，以使焊盘的阻抗与迹线的阻抗基本匹配。