公开(公告)号：US07667480B2

公开(公告)日：2010-02-23

申请号：US12093232

申请日：2006-11-08

Applicant: Yasuhiro Okuda ,  Akihisa Hosoe ,  Taro Fujita

Inventor： Yasuhiro Okuda ,  Akihisa Hosoe ,  Taro Fujita

IPC: G01R31/02

CPC classification number: H01R13/03 ,  H01R4/04 ,  H01R11/01 ,  H01R43/0235 ,  H01R43/0249 ,  H01R43/0256 ,  H05K3/0035 ,  H05K3/326 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0156 ,  Y10T29/49204

Abstract: Provided is an anisotropic conductive sheet (8) having heat resistance and cold resistance and suitable for connection of electrodes. The anisotropic conductive sheet of the present invention has conductivity in the thickness direction, wherein the base film (1), which is a film made of synthetic resin having an electrical insulation property, has a plurality of holes (3) formed in the thickness direction, and the holes (3) are open to one main surface of the base film and closed to the other main surface, wherein a metal is adhered to the closed parts (2a) and the inner walls (2b) of the holes (3) so that by contacting electrodes (7) with the closed parts (2a) respectively from the outside, the electrodes (7) can electrically be connected through the adhered metal to the main surface where the holes (3) are open.

Abstract translation: 提供具有耐热性和耐寒性并适合于连接电极的各向异性导电片（8）。 本发明的各向异性导电片在厚度方向上具有导电性，其中，作为由具有电绝缘性的合成树脂制成的膜的基膜（1）具有沿厚度方向形成的多个孔（3） 并且孔（3）对基膜的一个主表面开放并且与另一个主表面闭合，其中金属粘附到孔（3）的封闭部分（2a）和内壁（2b） 使得通过从外部分别将电极（7）与闭合部分（2a）接触，电极（7）可以通过粘附的金属电连接到孔（3）打开的主表面。

公开(公告)号：US20100032200A1

公开(公告)日：2010-02-11

申请号：US12581205

申请日：2009-10-19

Applicant: Naohiro HIROSE ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

Inventor： Naohiro HIROSE ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC: H05K1/11

CPC classification number: H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a motherboard and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract translation: 一种包含衬底的封装衬底310，该衬底设置有导体层5，导电连接销100被布置成与主板建立电连接并固定到衬底的表面，其中提供用于固定导电连接销的焊盘16，用于 封装衬底310.衬垫16被具有开口18的有机树脂绝缘层15覆盖，衬垫16通过该开口局部暴露于外部。 导电连接销100通过导电粘合剂17通过开口固定到暴露于外部的焊盘，从而防止例如当执行安装时发生例如导电连接销100从基板的溶液。

公开(公告)号：US20100012367A1

公开(公告)日：2010-01-21

申请号：US11722342

申请日：2005-12-14

Applicant: Marc Andre De Samber ,  Koen Van Os

Inventor： Marc Andre De Samber ,  Koen Van Os

IPC: H05K1/11

CPC classification number: H05K1/0206 ,  H05K1/0263 ,  H05K2201/09509 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/09781

Abstract: The present invention relates to a printed circuit board arrangement with a multi-layer substrate (1, 2) having a buried conductor (4) and a contact area (3), connected to the conductor (4) and being disposed on a surface of the substrate. In order to improve the cooling of the buried conductor, a metal cooling area (6) is provided above the conductor (4), and is connected to the conductor by means of one or more via conductors (7).

Abstract translation: 本发明涉及具有多层衬底（1,2）的印刷电路板装置，该多层衬底具有埋入导体（4）和与该导体（4）连接的接触区域（3） 底物。 为了改善掩埋导体的冷却，金属冷却区域（6）设置在导体（4）上方，并通过一个或多个通孔导体（7）与导体连接。

公开(公告)号：US07617598B2

公开(公告)日：2009-11-17

申请号：US11681964

申请日：2007-03-05

Applicant: Anthony Primavera ,  Steven P. Findell

Inventor： Anthony Primavera ,  Steven P. Findell

IPC: H01K3/10

CPC classification number: H05K1/0271 ,  H05K1/0201 ,  H05K1/0269 ,  H05K1/0272 ,  H05K1/115 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09509 ,  H05K2203/161 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: This document discusses, among other things, a method including providing a laminate having a first conductive layer, a second conductive layer and an insulator between the first and second conductive layers. A hollow conductive via is formed through the insulator, the conductive via electrically connects the first and second conductive layers. At least one conductive trace electrically connects the hollow conductive via to at least one of the first and second conductive layers. The method further includes forming a channel in the insulator adjacent to the hollow conductive via and the channel surrounds the via. Wherein the channel extends at least part way between the first and second conductive layers, the at least one conductive trace bridges the channel, and the via is isolated from the insulator by the surrounding channel formed adjacent to the hollow conductive via. The via is isolated to prevent separation between the hollow conductive via and at least one of the first and second conductive layers, where the insulator is in a swollen condition.

Abstract translation: 本文件尤其涉及一种包括提供在第一和第二导电层之间具有第一导电层，第二导电层和绝缘体的层压体的方法。 通过绝缘体形成中空导电通孔，导电通孔电连接第一和第二导电层。 至少一个导电迹线将中空导电通孔电连接到第一和第二导电层中的至少一个。 该方法还包括在绝缘体中邻近中空导电通孔形成通道，并且通道围绕通孔。 其中通道至少部分地在第一和第二导电层之间延伸，至少一个导电迹线桥接通道，并且通过与中空导电通孔相邻形成的周围通道将通孔与绝缘体隔离。 通孔被隔离以防止中空导电通孔与绝缘体处于膨胀状态的第一和第二导电层中的至少一个之间的分离。

公开(公告)号：US20090243076A1

公开(公告)日：2009-10-01

申请号：US12414502

申请日：2009-03-30

Applicant: Peter C. Salmon

Inventor： Peter C. Salmon

IPC: H01L23/50 ,  H01L23/488 ,  H01L23/522

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括轨迹宽度为5微米或更小的柔性多层互连电路。 用于制造液晶显示器，LCD，面板的玻璃面板制造设备用于制造互连电路。 在具有中间剥离层的玻璃载体上形成聚合物基层。 金属和电介质的交替层形成在基底层上，并被图案化以在玻璃面板上产生多层互连电路阵列。 在互连电路上沉积一层聚合物，并在输入/输出（I / O）焊盘位置形成开口。 将焊膏沉积在开口中以形成填充有焊料的孔。 在切割玻璃载体以形成分离的互连电路之后，使用倒装芯片接合对IC芯片进行螺柱凸起并组装，其中部件上的螺柱凸起插入到互连电路上的对应的孔中。 对IC芯片进行测试和返工以形成测试电路组件。 描述了连接到测试仪和其他模块和电子系统的方法。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器实施例。

公开(公告)号：US20090229876A1

公开(公告)日：2009-09-17

申请号：US12401141

申请日：2009-03-10

Applicant: Michimasa Takahashi

Inventor： Michimasa Takahashi

IPC: H05K9/00 ,  H05K1/00 ,  H05K3/10

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: A flexible wiring board includes a first flexible base material with a conductor pattern formed thereon, a second flexible base material disposed adjacent to the first flexible base material and an insulating layer covering the first flexible base material and the second flexible base material. The insulating layer exposes at least one portion of the first flexible base material. A conductor pattern is formed on the insulating layer, and a plating layer is provided connecting the conductor pattern of the first flexible base material and the conductor pattern on the insulating layer.

Abstract translation: 柔性布线板包括：形成有导体图案的第一柔性基底材料，邻近第一柔性基底材料设置的第二柔性基底材料和覆盖第一柔性基底材料和第二柔性基底材料的绝缘层。 绝缘层暴露第一柔性基材的至少一部分。 在绝缘层上形成导体图案，并且在绝缘层上连接第一柔性基底材料的导体图形和导体图案的镀层。

公开(公告)号：US20090200073A1

公开(公告)日：2009-08-13

申请号：US12203340

申请日：2008-09-03

Applicant: Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

Inventor： Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

IPC: H05K1/16 ,  G03F7/20 ,  H05K3/30

CPC classification number: H05K1/162 ,  H05K3/0044 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09845 ,  H05K2203/025 ,  H05K2203/1476

Abstract: A printed wiring board includes a capacitor including a dielectric body having a first surface and a second surface, a first electrode provided on the first surface of the dielectric body, and a second electrode provided on the second surface of the dielectric body. The first electrode has an area facing and being smaller than the first surface of the dielectric body, and the second electrode has an area facing and being larger than the second surface of the dielectric body.

Abstract translation: 印刷布线板包括电容器，其包括具有第一表面和第二表面的电介质体，设置在电介质体的第一表面上的第一电极和设置在电介质体的第二表面上的第二电极。 第一电极具有面向并小于电介质体的第一表面的面积，并且第二电极具有面向并大于电介质体的第二表面的面积。

公开(公告)号：US07570491B2

公开(公告)日：2009-08-04

申请号：US10728591

申请日：2003-12-04

Applicant: Seok-Kyu Lee ,  Byoung-Youl Min ,  Chang-Hyun Nam ,  Hyun-Ju Jin ,  Jang-Kyu Kang

Inventor： Seok-Kyu Lee ,  Byoung-Youl Min ,  Chang-Hyun Nam ,  Hyun-Ju Jin ,  Jang-Kyu Kang

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/09509 ,  H05K2203/1461

Abstract: Disclosed herein is a printed circuit board with embedded capacitors therein which comprises inner via holes filled with a high dielectric polymer capacitor paste composed of a composite of BaTiO3 and an epoxy resin, and a process for manufacturing the printed circuit board.

Abstract translation: 这里公开了一种其中具有嵌入式电容器的印刷电路板，其包括填充有由BaTiO 3和环氧树脂的复合材料组成的高介电聚合物电容器糊的内部通孔，以及用于制造印刷电路板的工艺。

公开(公告)号：US07564116B2

公开(公告)日：2009-07-21

申请号：US12016919

申请日：2008-01-18

Applicant: Jin Yong Ahn ,  Cheol Seong Hwang ,  Sung Kun Kim ,  Chang Sup Ryu ,  Suk-Hyeon Cho ,  Ho Sik Jeon

Inventor： Jin Yong Ahn ,  Cheol Seong Hwang ,  Sung Kun Kim ,  Chang Sup Ryu ,  Suk-Hyeon Cho ,  Ho Sik Jeon

IPC: H01L29/00 ,  H05K3/30 ,  H01L21/20

CPC classification number: H05K1/162 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/108 ,  H05K3/244 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09881 ,  Y10S438/957 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract translation: 具有嵌入式电容器的印刷电路板包括：包含形成在其外层中的第一电路层的双面覆铜层压板，所述第一电路层包括底部电极和电路图案; 通过原子层沉积在第一电路层上沉积氧化铝膜而形成的介电层; 形成在电介质层上并包括顶电极和电路图案的第二电路层; 形成在第二电路层上的单面覆铜层压板; 盲孔通孔和形成在单面覆铜层压板的预定部分中的通孔; 以及形成在盲通孔和通孔中的镀层。 还公开了印刷电路板的制造方法。

公开(公告)号：US20090152715A1

公开(公告)日：2009-06-18

申请号：US11957101

申请日：2007-12-14

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device is made by first forming a protective layer over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件通过首先在半导体晶片的有效表面上形成保护层来制造。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。