公开(公告)号：US20030007292A1

公开(公告)日：2003-01-09

申请号：US09456746

申请日：1999-12-07

Applicant: Seagate technology LLC

Inventor： ADAM KARL HIMES ,  KEVIN JON SCHULZ

IPC: G11B005/48

CPC classification number: H05K1/028 ,  G11B5/4826 ,  G11B5/484 ,  G11B5/4853 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09736

Abstract: A printed circuit head interconnect of a head gimbal assembly (HGA) has different material thicknesses in different regions of the printed circuit head interconnect. The printed circuit head interconnect includes a lamination sheet of materials having dielectric materials and conductive materials. The regions which need to have a lower stiffness are made thinner than the rest of the regions. The rest of the regions are made thick and robust enough to support the HGA. A method of reducing the thicknesses of the printed circuit head interconnect includes applying a resist mask pattern having a plurality of openings with different sizes so as to obtain different thicknesses of the materials in different regions of the printed circuit head interconnect.

Abstract translation: 头万向节组件（HGA）的印刷电路头互连在印刷电路头互连的不同区域中具有不同的材料厚度。 印刷电路头互连件包括具有介电材料和导电材料的材料层压片。 需要具有较低刚度的区域比其余区域薄。 其余的区域制作得足够坚固，足以支持HGA。 减小印刷电路头互连的厚度的方法包括施加具有不同尺寸的多个开口的抗蚀剂掩模图案，以便在印刷电路头互连的不同区域中获得不同厚度的材料。

公开(公告)号：US20020027021A1

公开(公告)日：2002-03-07

申请号：US09928441

申请日：2001-08-14

Applicant: FUJITSU LIMITED

Inventor： Kazuhiko Tokuda

IPC: H05K007/02 ,  H05K007/06

CPC classification number: H05K1/0265 ,  H01R13/6461 ,  H01R13/6474 ,  H05K1/0216 ,  H05K1/095 ,  H05K3/06 ,  H05K3/061 ,  H05K3/1216 ,  H05K3/22 ,  H05K3/247 ,  H05K2201/035 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2201/10689 ,  H05K2203/0557

Abstract: A printed circuit board includes a first wiring line and a second wiring line spaced apart from the first wiring line. The first wiring line has a first portion having a surface which faces the second wiring line and is smaller in area than that of the second portion, so that a crosstalk noise between the first portion of the first wiring line and the second wiring line can be reduced.

公开(公告)号：US06323439B1

公开(公告)日：2001-11-27

申请号：US09386334

申请日：1999-08-31

Applicant: Rokuro Kambe ,  Toru Matsuura

Inventor： Rokuro Kambe ,  Toru Matsuura

IPC: H01R909

CPC classification number: H05K3/429 ,  H05K3/0038 ,  H05K3/44 ,  H05K3/4608 ,  H05K2201/09454 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49165

Abstract: A multilayer resin wiring board includes a metal core substrate having a first main surface and a second main surface; a plurality of wiring layers located on the first and second main surfaces of the metal core substrate; a plurality of insulating resin layers, each intervening between the metal core substrate and the wiring layers and between the metal core substrate and the wiring layers and between the wiring layers; and a via formed on the wall of a through hole for connection to the metal core substrate extending through the insulating resin layers and the metal core substrate so as to establish electrical conductivity to the metal core substrate. The metal core substrate has a thin portion which is thinner than the remaining portion of the metal core substrate. The through hole for connection to the metal core substrate is formed through the thin portion by laser machining.

Abstract translation: 多层树脂配线板包括具有第一主表面和第二主表面的金属芯基板; 位于金属芯基板的第一和第二主表面上的多个布线层; 多个绝缘树脂层，各自介于金属芯基板和布线层之间，金属芯基板和布线层之间以及布线层之间; 以及形成在通孔的壁上的通孔，用于连接到延伸穿过绝缘树脂层和金属芯基板的金属芯基板，以便建立对金属芯基板的导电性。 金属芯基板具有比金属芯基板的剩余部分薄的薄部。 用于连接到金属芯基板的通孔通过激光加工形成在薄部分上。

公开(公告)号：US06251704B1

公开(公告)日：2001-06-26

申请号：US09285656

申请日：1999-04-05

Applicant: Shinji Ohuchi ,  Yoshimi Egawa ,  Noritaka Anzai

Inventor： Shinji Ohuchi ,  Yoshimi Egawa ,  Noritaka Anzai

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0384 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4007 ,  H05K2201/0191 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A metal is formed at a rear surface of a substrate, the substrate also having a front surface at which a molded semiconductor chip is mounted. The metal pattern is covered with an insulating film, except for at a connecting area. A solder ball is bonded to the connecting area. The area of the metal pattern other than the connecting area inclines toward the substrate and gradually becomes thinner toward the outside thereof. Stress, which is applied to the solder ball, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks is reduced, and the solder ball which is used to achieve connection with an external substrate, is effectively prevented form becoming electrically disconnected.

Abstract translation: 在基板的背面形成有金属，该基板也具有安装模制的半导体芯片的前表面。 除了在连接区域之外，金属图案被绝缘膜覆盖。 焊球接合到连接区域。 连接区域以外的金属图案的面积朝向基板倾斜，并且朝向其外侧逐渐变薄。 应用于焊球的应力沿对角线方向施加并分散。 结果，减少了裂纹的发生次数，并且有效地防止了用于实现与外部基板的连接的焊球，从而形成电断开。

公开(公告)号：US6018197A

公开(公告)日：2000-01-25

申请号：US958083

申请日：1997-10-27

Applicant: Hajime Saiki ,  Kozo Yamasaki

Inventor： Hajime Saiki ,  Kozo Yamasaki

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H05K1/111 ,  H05K3/3436 ,  H01L2224/16 ,  H05K2201/0373 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/048 ,  Y02P70/611 ,  Y02P70/613

Abstract: A wired ceramic board has on a main surface of a ceramic substrate thereof a plurality of bonding pads each of which has a projection having a solderable outer surface and positioned inside an outer periphery of each bonding pad when observed in a plan view. To each bonding pad is bonded a solder ball by using solder which is lower in melting point than the solder ball. The ceramic board and a resinous printed board are placed one upon another in such a manner that their bonding pads are aligned with each other. The bonding pads are soldered together with low melting point solder. The projection of each bonding pad is embedded in or surrounded by a mass of low melting point solder and joined with the mass of solder to constitute an integral unit while serving as a core of the unit. A shearing force acting on the assembly of the ceramic board and the plastic or resinous board parallel to the main surface of the ceramic board due to a temperature variation is applied by way of the mass of solder to the projection to be supported thereby, whereby to prevent initiation and growth of a crack or cracks in the mass of solder.

Abstract translation: 有线陶瓷板在其陶瓷基板的主表面上具有多个接合焊盘，每个接合焊盘在平面图中观察时，每个焊盘具有可焊接的外表面并位于每个接合焊盘的外周的内部的突起。 通过使用熔点低于焊锡球的焊料，对每个焊盘焊接焊球。 陶瓷板和树脂印刷电路板以这样的方式彼此对准，使得它们的焊盘彼此对准。 焊盘与低熔点焊料焊接在一起。 每个接合焊盘的突出部分嵌入或被一群低熔点焊料围绕，并且与焊料块接合以构成整体单元，同时用作该单元的核心。 由于温度变化而作用于陶瓷板和陶瓷板的主表面平行的塑料或树脂板的剪切力通过焊料的质量被施加到要被支撑的突起上，由此 防止焊料质量发生裂缝或裂缝的起始和生长。

公开(公告)号：US5541369A

公开(公告)日：1996-07-30

申请号：US464567

申请日：1995-06-05

Applicant: Hiroshi Tahara ,  Seiju Kobayashi ,  Hitoshi Ohta

Inventor： Hiroshi Tahara ,  Seiju Kobayashi ,  Hitoshi Ohta

IPC: H05K1/02 ,  H05K1/00 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/118 ,  H05K2201/0784 ,  H05K2201/09727 ,  H05K2201/09736

Abstract: A printed circuit board having juxtaposed thereon in parallel plural conductive paths, at least a part of which has a different length, extending from one end side to the other end side, wherein the electric resistances of the conductive paths are made substantially same by changing the width of at least a part of the conductive paths.

Abstract translation: 一种印刷电路板，其平行地并置有多个导电路径，其至少一部分具有不同的长度，从一端侧延伸到另一端侧，其中通过改变导电路径使导电路径的电阻基本相同 至少一部分导电路径的宽度。

公开(公告)号：US5353499A

公开(公告)日：1994-10-11

申请号：US92883

申请日：1993-07-19

Applicant: Hisao Hattori ,  Tomohiko Ihara ,  Hiroshi Yoshino ,  Shosaku Yamanaka

Inventor： Hisao Hattori ,  Tomohiko Ihara ,  Hiroshi Yoshino ,  Shosaku Yamanaka

IPC: H01L21/3205 ,  H01L21/48 ,  H01L21/768 ,  H01L23/12 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H05K1/02 ,  H05K1/03 ,  H05K3/46 ,  H01K3/10

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/5383 ,  H05K1/0224 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0253 ,  H05K1/0306 ,  H05K2201/0154 ,  H05K2201/09018 ,  H05K2201/09681 ,  H05K2201/09736 ,  H05K3/4644 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/31678

Abstract: A method of forming a multilayered wiring board having a multilayered wiring structure includes the steps of forming a first mesh wiring layer having a plurality of holes therein, and forming a second wiring layer having a plurality of wirings undulating up and down so as to descend into the holes formed in the first wiring layer. In another method, the first wiring layer is formed with a plurality of protrusions and the wirings of the second wiring layer are formed between the protrusions. In the wiring boards formed according to the methods of the present invention, crosstalk between the wirings is suppressed.

Abstract translation: 一种形成具有多层布线结构的多层布线板的方法包括以下步骤：在其中形成具有多个孔的第一网状布线层，并形成具有上下波动的多条布线的第二布线层，以便下降 形成在第一布线层中的孔。 在另一方法中，第一布线层形成有多个突起，并且第二布线层的布线形成在突起之间。 在根据本发明的方法形成的布线板中，布线之间的串扰被抑制。

公开(公告)号：US4920363A

公开(公告)日：1990-04-24

申请号：US293823

申请日：1989-01-04

Applicant: James R. Hack

Inventor： James R. Hack

IPC: B41J2/395 ,  H05K1/00 ,  H05K1/11 ,  H05K3/46

CPC classification number: B41J2/395 ,  H05K1/117 ,  H05K1/0289 ,  H05K2201/0919 ,  H05K2201/09736 ,  H05K3/4644

Abstract: The method of manufacturing an electrostatic printhead or the like. Conductive surfaces are applied to both sides of an insulating substrate. Unneeded portions of the conductive surface are etched away by a photolithographic process to form conductive layers in patterns of parallel, spaced, printwire traces and connective conductors with ends of the printwire traces terminating in a common plane defining a printface of the printhead. Additional conductive material is added to the printwire traces by an additive plating process to give them a substantially square cross-section. The edge is laser trimmed to form the print face. Insulative layers are added over both sides with vias located over the connective conductors at places where electrical connection is to take place. A plurality of conductive busses are then formed on the insulative layers crossing over the connective conductors and vias with conductive material formed in the vias to make the desired electrical connections between the connective conductors and the busses.

Abstract translation: 静电打印头等的制造方法。 将导电表面施加到绝缘基板的两侧。 通过光刻工艺蚀刻掉导电表面的不需要的部分，以形成平行的，间隔开的印刷线迹线的图案中的导电层，并且连接导体与打印线迹线的端部终止于限定打印头的打印面的共同平面。 通过添加电镀工艺将附加的导电材料添加到印刷线迹线，以给它们基本上正方形的横截面。 边缘被激光修剪以形成打印面。 绝缘层通过两侧添加，其中通孔位于连接导体上，并在电连接处。 然后，在绝缘层上形成多个导电总线，该绝缘层穿过形成在通孔中的导电材料的连接导体和通孔，以形成连接导体和总线之间的所需电连接。

公开(公告)号：US4423467A

公开(公告)日：1983-12-27

申请号：US216745

申请日：1980-12-15

Applicant: Joseph M. Shaheen

Inventor： Joseph M. Shaheen

IPC: H05K1/11 ,  H05K3/34 ,  H05K7/10 ,  H05K1/18

CPC classification number: H05K7/1053 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09736 ,  H05K2201/10727 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613

Abstract: The invention comprises a connection array for establishing a plurality of electrical connections between circuit pads of a support, such as a circuit board, and contacts of an electrical housing, such as a hermetic chip carrier, wherein the contacts comprise semi-circular vertical indentations in the housing periphery with each indentation having a conductive layer therein. A plurality of pillars, which may be electroplated, extend vertically above the support in an array respectively corresponding to the outline of the indentations with each pillar being connected to different pad of the support and the pillars having dimensions to permit at least partial entry into the indentations whereby solder may be introduced between the pillars and associated conductive layers to establish visible and inspectable electrical connections therebetween.

Abstract translation: 本发明包括用于在诸如电路板的支撑件的电路板之间建立多个电连接的连接阵列和诸如密封芯片载体的电气外壳的触点，其中触点包括半圆形垂直凹槽 每个凹陷的壳体周边在其中具有导电层。 可以电镀的多个柱子分别对应于凹槽的轮廓垂直地延伸在支撑件上方，每个支柱连接到支撑件的不同垫片上，并且支柱具有允许至少部分进入 从而可以在柱和相关的导电层之间引入焊料以在其间建立可见和可检查的电连接。

公开(公告)号：US4312897A

公开(公告)日：1982-01-26

申请号：US157595

申请日：1980-06-09

Applicant: William G. Reimann

Inventor： William G. Reimann

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42 ,  H05K3/18

CPC classification number: H05K3/243 ,  H05K1/0265 ,  H05K3/062 ,  H05K3/427 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0384 ,  H05K2203/0574 ,  H05K3/108 ,  H05K3/3473

Abstract: Narrow conductors and narrow spaces therebetween, typically two or three mils wide, are fabricated on outer layers of a printed wiring board with built-up areas such as plated-through holes or conductors of widths greater than two or three mils. Gold is deposited over a copper clad substrate in a pattern defining the desired circuitry. Thereafter, solder is placed at the built-up areas and, using both the solder and the gold as resist or masks, the exposed copper is removed by etching. An organic resist material is used in lieu of solder when the built-up area comprises wide conductors or leads, e.g., power busses.

Abstract translation: 典型地为2或3密耳宽的窄导体和狭窄的空间被制造在印刷线路板的外层上，其具有诸如电镀通孔或宽度大于2或3密耳的导体的组合区域。 金以限定所需电路的图案沉积在铜包覆基板上。 此后，将焊料放置在积聚区域，并且使用焊料和金作为抗蚀剂或掩模，通过蚀刻去除暴露的铜。 当组合区域包括宽导体或引线（例如功率总线）时，使用有机抗蚀剂材料代替焊料。