公开(公告)号：US09468101B2

公开(公告)日：2016-10-11

申请号：US14659977

申请日：2015-03-17

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： Kuo-Fu Su ,  Gwun-Jin Lin

IPC: H05K1/00 ,  H05K1/11 ,  H05K1/09 ,  H05K3/40 ,  H05K3/06

CPC classification number: H05K1/115 ,  H05K1/0251 ,  H05K1/092 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4069 ,  H05K2201/0397 ,  H05K2201/09845 ,  H05K2201/09854

Abstract: Disclosed urea microvia structure of a flexible circuit board and a manufacturing method thereof. A first through hole is formed in a first conductive layer of a flexible circuit board and a first exposed zone is defined. A second conductive layer includes a second through hole formed therein and defines a second exposed zone. A dielectric layer includes a dielectric layer through hole corresponding to the second through hole of the second conductive layer. A conductive paste layer is filled in the second through hole of the second conductive layer, the dielectric layer through hole of the dielectric layer, and the first through hole of the first conductive layer in such a way that the conductive paste layer covers and electrically contacts the first exposed zone of the first conductive layer and the second exposed zone of the second conductive layer.

Abstract translation: 柔性电路板的尿素微孔结构及其制造方法。 在柔性电路板的第一导电层中形成第一通孔，并且限定第一暴露区域。 第二导电层包括形成在其中的第二通孔并且限定第二暴露区域。 电介质层包括与第二导电层的第二通孔对应的电介质层通孔。 导电膏层填充在第二导电层的第二通孔，电介质层的电介质层通孔和第一导电层的第一通孔中，导电膏层覆盖并电接触 第一导电层的第一暴露区域和第二导电层的第二暴露区域。

公开(公告)号：US09443788B2

公开(公告)日：2016-09-13

申请号：US13966633

申请日：2013-08-14

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H05K1/11 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H05K3/42 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/01079

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

Abstract translation: 一种制造通孔电极基板的方法包括在基板上形成多个通孔，通过在多个通孔中填充导电材料形成多个通孔电极，在一个通孔上形成第一绝缘层 在所述第一绝缘层上形成多个第一开口，所述多个第一开口将与所述多个通孔电极中的每一个相对应的多个通孔电极暴露在所述第一绝缘层上，并且使用所述关系来校正所述多个第一开口的位置 在多个通孔中的倾斜通孔的打开位置的测量距离值的偏移量与多个通孔中的倾斜通孔的打开位置的设计距离值之间， 相对于基板的中心位置。

公开(公告)号：US09425137B2

公开(公告)日：2016-08-23

申请号：US14552771

申请日：2014-11-25

Applicant: IBIDEN CO., LTD.

Inventor： Nobuyuki Naganuma ,  Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01L23/053 ,  H01L23/12 ,  H05K1/11 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46 ,  H05K1/02 ,  H05K1/09 ,  H05K1/18 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/116 ,  H05K1/18 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/4069 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09854 ,  Y10T156/1056

Abstract: A wiring board includes multiple insulating layers including first, second, third, fourth and fifth insulation layers laminated in the order of the first, second, third, fourth and fifth insulation layers. The first insulation layer has a first conductor including plating, the second insulation layer has a second conductor including plating, the third insulation layer has a third conductor including conductive paste, the fourth insulation layer has a fourth conductor including plating, the fifth insulation layer has a fifth conductor including plating, and the first conductor, the second conductor, the third conductor, the fourth conductor and the fifth conductor are formed along the same axis and are electrically continuous with each other.

Abstract translation: 布线板包括多个绝缘层，包括以第一，第二，第三，第四和第五绝缘层的顺序层叠的第一，第二，第三，第四和第五绝缘层。 所述第一绝缘层具有包括电镀的第一导体，所述第二绝缘层具有包括电镀的第二导体，所述第三绝缘层具有包括导电糊的第三导体，所述第四绝缘层具有包括电镀的第四导体，所述第五绝缘层具有 包括电镀的第五导体，并且第一导体，第二导​​体，第三导体，第四导体和第五导体沿着相同的轴线形成并且彼此电连接。

公开(公告)号：US09420708B2

公开(公告)日：2016-08-16

申请号：US13427231

申请日：2012-03-22

Applicant: Toshiaki Hibino ,  Takema Adachi

Inventor： Toshiaki Hibino ,  Takema Adachi

IPC: H01K3/10 ,  H05K3/46 ,  H05K3/44 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/4608 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/445 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09854 ,  Y10T29/49124

Abstract: A method for manufacturing a printed wiring board includes preparing a core substrate having a metal layer having a first penetrating hole and insulation layers formed on the metal layer such that the metal layer is interposed between the insulation layers, forming in the core substrate a second penetrating hole having a first opening portion aligned with the first penetrating hole on a first-surface side of the core substrate and a second opening portion aligned with the first penetrating hole on a second-surface side of the core substrate, forming a first conductor on a first surface of the core substrate, forming a second conductor on a second surface of the core substrate on the opposite side of the first surface of the core substrate, and filling a conductive material in the second penetrating hole such that a through-hole conductor connecting the first conductor and the second conductor is formed.

Abstract translation: 一种制造印刷电路板的方法，包括制备具有第一穿透孔的金属层和形成在金属层上的绝缘层的芯基板，使得金属层插入在绝缘层之间，在芯基板中形成第二穿透 在芯基板的第一表面侧具有与第一贯通孔对准的第一开口部和与芯基板的第二表面侧的第一贯通孔对准的第二开口部， 在芯基板的第一表面上，在芯基板的第一表面的相对侧上的芯基板的第二表面上形成第二导体，并且在第二贯穿孔中填充导电材料，使得连接 形成第一导体和第二导体。

公开(公告)号：US20160192490A1

公开(公告)日：2016-06-30

申请号：US14966518

申请日：2015-12-11

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Myung-Sam KANG ,  Young-Gwan KO ,  Sang-Hoon KIM ,  Kang-Wook BONG ,  Hye-Won JUNG ,  Yong-Wan JI

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/03

CPC classification number: H05K1/115 ,  H05K1/0326 ,  H05K1/0346 ,  H05K3/0023 ,  H05K3/426 ,  H05K3/428 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/1476

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes an insulating layer including a first resin layer and a second resin layer, circuit layers disposed on upper and lower surfaces of the insulating layer, and a via configured to connect the circuit layer formed on the upper surface to the circuit layer formed on the lower surface, and the second resin layer extends from an upper surface of the first resin layer to a lower surface of the first resin layer by passing through the first resin layer as to contact a side surface of the via.

Abstract translation: 提供一种印刷电路板及其制造方法。 印刷电路板包括绝缘层，其包括第一树脂层和第二树脂层，设置在绝缘层的上表面和下表面上的电路层，以及通孔，被配置为将形成在上表面上的电路层连接到电路层 形成在下表面上，第二树脂层通过第一树脂层从第一树脂层的上表面延伸到第一树脂层的下表面，以接触通孔的侧表面。

公开(公告)号：US20160183371A1

公开(公告)日：2016-06-23

申请号：US14659977

申请日：2015-03-17

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： KUO-FU SU ,  GWUN-JIN LIN

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/06 ,  H05K1/09

CPC classification number: H05K1/115 ,  H05K1/0251 ,  H05K1/092 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4069 ,  H05K2201/0397 ,  H05K2201/09845 ,  H05K2201/09854

Abstract: Disclosed urea microvia structure of a flexible circuit board and a manufacturing method thereof. A first through hole is formed in a first conductive layer of a flexible circuit board and a first exposed zone is defined. A second conductive layer includes a second through hole formed therein and defines a second exposed zone. A dielectric layer includes a dielectric layer through hole corresponding to the second through hole of the second conductive layer. A conductive paste layer is filled in the second through hole of the second conductive layer, the dielectric layer through hole of the dielectric layer, and the first through hole of the first conductive layer in such a way that the conductive paste layer covers and electrically contacts the first exposed zone of the first conductive layer and the second exposed zone of the second conductive layer.

Abstract translation: 柔性电路板的尿素微孔结构及其制造方法。 在柔性电路板的第一导电层中形成第一通孔，并且限定第一暴露区域。 第二导电层包括形成在其中的第二通孔并且限定第二暴露区域。 电介质层包括与第二导电层的第二通孔对应的电介质层通孔。 导电膏层填充在第二导电层的第二通孔，电介质层的电介质层通孔和第一导电层的第一通孔中，导电膏层覆盖并电接触 第一导电层的第一暴露区域和第二导电层的第二暴露区域。

公开(公告)号：US20160150633A1

公开(公告)日：2016-05-26

申请号：US14947091

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Marc B. Cartier, JR.

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11 ,  H01R43/20

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

Abstract translation: 印刷电路板包括多个层，包括附着层和布线层; 以及形成在所述多个层中的通孔图案，所述通孔图案中的每一个包括：形成差分信号对的双直径第一和第二信号通孔，所述第一和第二信号通孔被配置为接纳连接器的信号导体的接触尾部; 与第一和第二信号通孔中的每一个相邻的双直径地面阴影通孔，其中双直径阴影接地通孔相对于双直径第一和第二信号通孔具有反向直径构型; 以及配置为接受连接器的接地导体的接触尾部的接地通孔。

公开(公告)号：US09350124B2

公开(公告)日：2016-05-24

申请号：US14408039

申请日：2013-03-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H01R12/68 ,  H01R12/50 ,  H01R13/24 ,  H01R12/82 ,  H05K3/36 ,  H05K3/40 ,  H01R12/73 ,  H01L23/00 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。

公开(公告)号：US20160135289A1

公开(公告)日：2016-05-12

申请号：US14875241

申请日：2015-10-05

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Suk Hyeon CHO ,  Yoong OH ,  Young Gwan KO ,  Yong Ho BAEK ,  Young Kuk KO

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/15788 ,  H05K1/038 ,  H05K1/115 ,  H05K1/181 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0909 ,  H05K2201/09536 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10674

Abstract: There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board include a glass plate, an insulating member penetrating through the glass plate, insulating layers disposed on a first surface and a second surface of the glass plate, and a via through the insulating member.

Abstract translation: 提供了一种印刷电路板及其制造方法。 印刷电路板包括玻璃板，穿透玻璃板的绝缘构件，设置在玻璃板的第一表面和第二表面上的绝缘层，以及通过绝缘构件的通孔。

公开(公告)号：US09320143B2

公开(公告)日：2016-04-19

申请号：US13845325

申请日：2013-03-18

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Cheng-Ming Weng ,  Wei-Ming Cheng ,  Han-Pei Huang

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K3/0032 ,  H05K3/42 ,  H05K3/426 ,  H05K2201/09563 ,  H05K2201/09709 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49165

Abstract: A wiring board includes a substrate, a first conductor layer, a second conductor layer, and a through-via conductor. The substrate has a first surface, a second surface, and at least one through-via. The first conductor layer is formed on the first surface, and the second conductor layer is formed on the second surface. The through-via conductor is formed in the through-via for electrically connecting to the first conductor layer and the second conductor layer. The through-via has a first depressed portion exposed in the first surface, a second depressed portion exposed in the second surface, and a tunnel portion between the first depressed portion and the second depressed portion for connecting the first depressed portion and the second depressed portion. The first depressed portion and the second depressed, portion are non-coaxial.

Abstract translation: 布线基板包括基板，第一导体层，第二导体层和通孔导体。 衬底具有第一表面，第二表面和至少一个通孔。 第一导体层形成在第一表面上，第二导体层形成在第二表面上。 通孔导体形成在用于电连接到第一导体层和第二导体层的通孔中。 通孔具有暴露在第一表面中的第一凹陷部分，暴露在第二表面中的第二凹部，以及在第一凹陷部分和第二凹陷部分之间的用于连接第一凹陷部分和第二凹陷部分的隧道部分 。 第一凹陷部分和第二凹陷部分是非同轴的。