公开(公告)号：US20060261472A1

公开(公告)日：2006-11-23

申请号：US11435716

申请日：2006-05-18

Applicant: Junichi Kimura ,  Kazuhiko Honjo ,  Eiji Kawamoto ,  Shinji Harada ,  Motoyoshi Kitagawa

Inventor： Junichi Kimura ,  Kazuhiko Honjo ,  Eiji Kawamoto ,  Shinji Harada ,  Motoyoshi Kitagawa

IPC: H01L23/34

CPC classification number: H05K1/144 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/3436 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/10371 ,  H05K2201/10666 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A multilayer module which includes parts-containing module whose circuit board has been mounted at one surface with electronic component and the electronic component is covered with resin layer. Connection terminals have been provided either at resin layer or at the other surface of circuit board, also through hole has been provided for connection between the two surfaces of module. Also included is module, which has been provided with connection terminals at a place corresponding to connection terminal, and through hole for connection between the connection terminals and electronic component. Disposed between conductor layer and conductor layer is insulation layer, which insulation layer having conductive bond for connection between connection terminals, respectively. In the above-described configuration, places of through hole and electronic component in module are not restricted by a location of through hole.

Abstract translation: 一种多层模块，其包括其电路板已经在一个表面上安装有电子部件并且电子部件被树脂层覆盖的部件容纳模块。 已经在树脂层或电路板的另一表面设置了连接端子，并且还提供了用于在模块的两个表面之间连接的通孔。 还包括在对应于连接端子的位置处设置有连接端子的模块和用于连接端子和电子部件之间的连接的通孔。 在导体层和导体层之间设置绝缘层，绝缘层分别具有用于连接端子之间连接的导电接合层。 在上述结构中，模块中的通孔和电子部件的位置不受通孔的位置的限制。

公开(公告)号：US07119285B2

公开(公告)日：2006-10-10

申请号：US10790310

申请日：2004-03-01

Applicant: Deok-heung Kim ,  Bong-hui Lee

Inventor： Deok-heung Kim ,  Bong-hui Lee

IPC: H05K1/00 ,  H05K1/03

CPC classification number: H05K1/028 ,  H05K3/28 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10666

Abstract: A flexible printed circuit board (FPCB) which prevents a short circuit due to a crack in a bending portion is provided. The FPCB includes an end portion, a bending portion extended from the end portion, and a circuit portion extended from the bending portion. The improved FPCB includes a base film which is flexible and comprises a first via-hole formed adjacent to the end portion and the bending portion and a second via-hole formed adjacent to the bending portion and the circuit portion, a first conductive layer formed on an outer surface of at least the end portion and the bending portion, a cover layer formed on the first conductive layer, a second conductive layer which is formed on an inner surface of the end portion and is electrically connected to the first conductive layer through the first via-hole, and a third conductive layer which is formed on an inner surface of the extension circuit portion and is electrically connected to the first conductive layer through the second via-hole.

Abstract translation: 提供一种柔性印刷电路板（FPCB），其防止由于弯曲部分的裂纹引起的短路。 FPCB包括端部，从端部延伸的弯曲部和从弯曲部延伸的电路部。 改进的FPCB包括柔性的基膜，包括邻近端部和弯曲部分形成的第一通孔和邻近弯曲部分和电路部分形成的第二通孔，形成在第一导电层上的第一导电层 至少所述端部和所述弯曲部的外表面，形成在所述第一导电层上的覆盖层，形成在所述端部的内表面上并通过所述第一导电层电连接到所述第一导电层的第二导电层 第一导电孔和第三导电层，其形成在延伸电路部分的内表面上，并通过第二通孔与第一导电层电连接。

公开(公告)号：US20060066416A1

公开(公告)日：2006-03-30

申请号：US10950131

申请日：2004-09-24

Applicant: Dean Nicholson ,  Reto Zingg ,  Keith Howell ,  Eric Ehlers

Inventor： Dean Nicholson ,  Reto Zingg ,  Keith Howell ,  Eric Ehlers

IPC: H03H7/38

CPC classification number: H01L23/66 ,  H01L23/04 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01P1/20 ,  H05K1/0243 ,  H05K2201/10666 ,  H05K2201/10727 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In one aspect, a signal path is described. The signal path has a nominal impedance over a specified bandwidth and interconnects a port of a microwave circuit package and a microwave component mounted in the microwave circuit package. The signal path includes an inductive transition and first and second capacitive structures. The inductive transition extends from a first point on the signal path to a second point on the signal path and has an excess impedance above the nominal impedance. The first and second capacitive structures respectively shunt the first and second points on the signal path to compensate the excess impedance of the inductive transition. The inductive transition and the first and second capacitive structures approximate a filter having an impedance substantially matching the nominal impedance over the specified bandwidth. In other aspects, a microwave circuit package that incorporates the above-described signal path and an interconnection method that includes forming the above-described signal path are described.

Abstract translation: 在一个方面，描述信号路径。 信号路径具有指定带宽上的标称阻抗，并且互连微波电路封装的端口和安装在微波电路封装中的微波元件。 信号路径包括电感转换和第一和第二电容结构。 电感转换从信号路径上的第一点延伸到信号路径上的第二个点，并具有超过标称阻抗的过量阻抗。 第一和第二电容结构分别分流信号路径上的第一和第二点以补偿电感转变的过量阻抗。 感应跃迁以及第一和第二电容结构近似于具有与指定带宽上的标称阻抗基本匹配的阻抗的滤波器。 在其他方面，描述了结合上述信号路径的微波电路封装以及包括形成上述信号路径的互连方法。

公开(公告)号：US06897933B2

公开(公告)日：2005-05-24

申请号：US10096322

申请日：2002-03-12

Applicant: Kazushige Hoshina

Inventor： Kazushige Hoshina

IPC: G02F1/1345 ,  G02F1/13 ,  G09F9/00 ,  G09F9/30 ,  H05K1/14 ,  H05K3/32 ,  H05K3/36

CPC classification number: G02F1/13452 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0326 ,  H05K2201/10666

Abstract: A wiring substrate 7 is attached by pressure to a substrate overhang with an ACF 6b, and substrate terminals 21 formed on the substrate overhang 2c from ITO and the first terminals 21 formed on the rear surface of wiring substrate 7 are electrically connected. The wiring substrate 7 has second terminals 27 on its surface and these second terminals 27 are electrically connected to the first terminals located on the rear surface via a throughhole. The wiring pattern on the wiring substrate 7 is formed from a material with an electric resistance lower than that of the ITO forming the substrate terminals 21, which makes it possible to hold the resistance of the wiring on the substrate overhang 2c to a low value.

Abstract translation: 布线基板7通过ACF6b通过压力附接到基板突出部，并且形成在基板突出部2c上的基板端子21和形成在布线基板7的后表面上的第一端子21电连接。 布线基板7在其表面上具有第二端子27，并且这些第二端子27经由通孔与位于后表面的第一端子电连接。 布线基板7上的布线图形由电阻低于形成基板端子21的ITO的电阻的材料形成，这使得可以将基板突出部2c上的布线的电阻保持在低值 。

公开(公告)号：US20050056923A1

公开(公告)日：2005-03-17

申请号：US10953248

申请日：2004-09-28

Applicant: Mark Moshayedi

Inventor： Mark Moshayedi

IPC: H01L23/50 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01L29/00

CPC classification number: H05K1/181 ,  H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/0949 ,  H05K2201/10515 ,  H05K2201/10666 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. The multi-chip stack module comprises support structures alternating with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. Various embodiments disclose a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that common signals are connected in the stack and individually-accessed signals are separated within the stack.

Abstract translation: 多芯片堆叠模块为给定的表面芯片占用空间提供了增加的电路密度。 多芯片堆叠模块包括与标准表面安装型芯片交替的支撑结构，以形成堆叠，其中支撑结构将芯片电连接。 各种实施例公开了用于在垂直堆叠中互连多个大体上平坦的芯片的结构和方法，使得公共信号连接在堆栈中，并且单独访问的信号在堆栈内分离。

公开(公告)号：US06860003B2

公开(公告)日：2005-03-01

申请号：US10138139

申请日：2002-05-02

Applicant: Apurba Roy

Inventor： Apurba Roy

IPC: H01L23/498 ,  H01R4/02 ,  H01R12/00 ,  H01R12/52 ,  H01R12/57 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K5/00

CPC classification number: H01R12/57 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/52 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/1031 ,  H05K2201/10666 ,  H05K2201/10856 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49211 ,  H01L2924/00

Abstract: In accordance with the invention, a low impedance surface-mount connector comprises a length of cylindrical rod having an I-shaped cross section. The device permits interconnection by pick-and-place techniques, and the interconnection has advantageous qualities of low resistance, low inductance, mechanical compliance and ease of manufacture. A first circuit device having one or more circuit components is interconnected with a second circuit device by surface mounting such connectors on the first circuit device, providing corresponding solder pads on the second circuit device, and mounting the connectors of the first circuit device onto the pads of the second.

Abstract translation: 根据本发明，低阻抗表面安装连接器包括具有I形横截面的一定长度的圆柱形杆。 该器件允许通过拾取和放置技术进行互连，并且互连具有低电阻，低电感，机械符合性和易于制造的优点。 具有一个或多个电路部件的第一电路装置通过将这种连接器表面安装在第一电路装置上而与第二电路装置互连，在第二电路装置上提供相应的焊盘，并将第一电路装置的连接器安装到焊盘 的第二。

公开(公告)号：US20050006140A1

公开(公告)日：2005-01-13

申请号：US10478295

申请日：2002-05-18

Applicant: Dietmar Birgel ,  Sergej Lopatin

Inventor： Dietmar Birgel ,  Sergej Lopatin

IPC: H05K3/34 ,  H01L23/12 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28 ,  H05K3/32 ,  H05K3/36

CPC classification number: H05K3/363 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/114 ,  H05K3/28 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/09063 ,  H05K2201/0979 ,  H05K2201/10666 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655

Abstract: A circuit board having, between the circuit board and a component arranged thereon, an electrical and mechanical connection of high mechanical-load-bearing ability. The circuit board includes at least one internally situated conductor path, a first insulating layer arranged on a first surface of the circuit board, a second insulating layer arranged on a second surface of the circuit board, a first contact location at which the conductor path is accessible, a second contact location, at which the conductor path is accessible through a bore passing completely through the circuit board, and an electronic component arranged on the first surface. The component has a first contact surface, which is connected with the first contact location by solder or electrically conductive adhesive, and a second contact surface which is connected with the second contact location by solder or adhesive.

Abstract translation: 在电路板和布置在其上的部件之间具有高机械承载能力的电气和机械连接的电路板。 所述电路板包括至少一个内部定位的导体路径，布置在所述电路板的第一表面上的第一绝缘层，布置在所述电路板的第二表面上的第二绝缘层，所述导体路径为 可接近的第二接触位置，导体路径可以通过完全穿过电路板的孔访问，以及布置在第一表面上的电子部件。 该部件具有通过焊料或导电粘合剂与第一接触位置连接的第一接触表面，以及通过焊料或粘合剂与第二接触位置连接的第二接触表面。

公开(公告)号：US20040246092A1

公开(公告)日：2004-12-09

申请号：US10721478

申请日：2003-11-25

Inventor： Gregory A. Graves ,  Michael Mengruo Zhang ,  Daniel Chandler ,  Chi-Ming Chan ,  Shou-Mean Fang ,  Dennis Siden ,  Mark Thompson

IPC: H01C007/10

CPC classification number: H05K1/184 ,  H01C1/14 ,  H01C1/1406 ,  H01C7/027 ,  H01C17/06586 ,  H05K1/182 ,  H05K3/0097 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10469 ,  H05K2201/10643 ,  H05K2201/10666 ,  Y02P70/613 ,  Y10T29/49085 ,  Y10T29/49101 ,  Y10T29/49103

Abstract: An electrical device which comprises first and second laminar electrodes and a laminar PTC resistive element sandwiched between them, the device comprising (a) a main portion which comprises a main part of the first electrode, a main part of the second electrode, and a main part of the resistive element; and (b) a first connection leg which extends away from the main portion and which comprises a first leg part of the first electrode which is integral with the main part of the first electrode, and a first leg part of the resistive element which is integral with the main part of the resistive element. Such devices can be secured to circuit boards in a variety of ways, and to elastically deformed terminals. Preferably preferred devices contain two laminar electrodes, with a PTC element between them, and a cross-conductor which passes through the thickness of the device and contacts one only of the two electrodes. The cross-conductor permits connection to both electrodes from the same side of the device, and also makes it possible to carry out the steps for preparing such devices on an assembly which corresponds to a number of individual devices, with division of the assembly as the final step.

Abstract translation: 一种电气装置，包括第一和第二层状电极和夹在它们之间的层状PTC电阻元件，所述装置包括（a）主要部分，其包括第一电极的主要部分，第二电极的主要部分和主体部分 电阻元件的一部分; 和（b）第一连接腿，其远离主要部分延伸并且包括与第一电极的主要部分成一体的第一电极的第一腿部和电阻元件的第一腿部， 与电阻元件的主要部分。 这样的装置可以以各种方式固定到电路板，并且可弹性变形的端子。 优选地，优选的装置包含两个层状电极，其间具有PTC元件，并且穿过该器件的厚度并且仅与两个电极中的一个接触的交叉导体。 交叉导体允许从设备的同一侧连接到两个电极，并且还使得可以在对应于多个单独设备的组件上执行用于准备这样的设备的步骤，将组件划分为 最后一步。

公开(公告)号：US06815313B2

公开(公告)日：2004-11-09

申请号：US10033397

申请日：2001-12-27

Applicant: Hiromi Yatsuda

Inventor： Hiromi Yatsuda

IPC: H01L21301

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10666 ,  H05K2203/1147 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: A first substrate has a plurality of bumps and a second substrate has a plurality of openings at positions in registration with the plurality of bumps when the first and second substrates are placed one on top of the other in a confronting manner. The first and second substrates are put together by fusing a sealing wall formed on the second substrate, to hermetically seal an electronic device lying on the first substrate therein. Gas that may be generated upon fusing of the sealing wall can be effectively removed through the openings in the second substrate.

Abstract translation: 第一基板具有多个凸块，并且当第一和第二基板以相对的方式一个放置在另一个基板上时，第二基板在与多个凸块对准的位置处具有多个开口。 通过将形成在第二基板上的密封壁融合，将第一和第二基板放置在一起，将位于其上的第一基板上的电子设备密封。 可以通过第二基板中的开口有效地去除在密封壁融合时产生的气体。

公开(公告)号：US06722930B2

公开(公告)日：2004-04-20

申请号：US10138173

申请日：2002-05-02

Applicant: Apurba Roy

Inventor： Apurba Roy

IPC: H01R4050

CPC classification number: H01R12/57 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/52 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/1031 ,  H05K2201/10666 ,  H05K2201/10856 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49211 ,  H01L2924/00

Abstract: In accordance with the invention, a low impedance surface-mount connector comprises a length of cylindrical rod having an I-shaped cross section. The device permits interconnection by pick-and-place techniques, and the interconnection has advantageous qualities of low resistance, low inductance, mechanical compliance and ease of manufacture. A first circuit device having one or more circuit components is interconnected with a second circuit device by surface mounting such connectors on the first circuit device, providing corresponding solder pads on the second circuit device, and mounting the connectors of the first circuit device onto the pads of the second.

Abstract translation: 根据本发明，低阻抗表面安装连接器包括具有I形横截面的一定长度的圆柱形杆。 该器件允许通过拾取和放置技术进行互连，并且互连具有低电阻，低电感，机械符合性和易于制造的优点。 具有一个或多个电路部件的第一电路装置通过将这种连接器表面安装在第一电路装置上而与第二电路装置互连，在第二电路装置上提供对应的焊盘，并将第一电路装置的连接器安装到焊盘 的第二。