公开(公告)号：US20180005844A1

公开(公告)日：2018-01-04

申请号：US15633078

申请日：2017-06-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： HARUO SORIMACHI

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/73204 ,  H01L2924/15313 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2201/0979

Abstract: A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.

公开(公告)号：US09839118B2

公开(公告)日：2017-12-05

申请号：US15031369

申请日：2013-11-01

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)

Inventor： Bo Zhou ,  Junyou Chen ,  Kun Liu

IPC: H01P3/08 ,  H01P5/08 ,  H05K1/14 ,  H05K1/02 ,  H01Q1/38 ,  H01Q1/22 ,  H01Q1/48 ,  H05K3/10 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01L2924/19107 ,  H01P3/081 ,  H01P5/028 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/48 ,  H05K1/0213 ,  H05K1/025 ,  H05K1/117 ,  H05K1/14 ,  H05K1/142 ,  H05K3/10 ,  H05K3/4644 ,  H05K2201/04 ,  H05K2201/0979 ,  H05K2203/049

Abstract: A wide bandwidth circuit board arrangement includes two coplanar substrates separated by a predetermined gap, and at least one bond wire arranged across the gap and interconnecting a respective conducting microstrip line on a first side of each respective substrate. Further, the arrangement includes at least one open stub arrangement configured on the first side of each respective substrate, each open stub arrangement comprising a microstrip extending at an angle from an end of each conducting strip on each respective substrate. Finally, the arrangement includes a ground layer on a second side of each respective substrate, and a defected ground structure arranged on the second side of each respective substrate and laterally overlapping each respective open stub arrangement arranged on the first side.

公开(公告)号：US09763333B2

公开(公告)日：2017-09-12

申请号：US14642346

申请日：2015-03-09

Applicant: James Michael Parascandola

Inventor： James Michael Parascandola

IPC: H05K3/22 ,  H05K1/02

CPC classification number: H05K3/222 ,  H05K1/029 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10106

Abstract: The electrical circuit can include a line circuit portion having a number of shared resistor pads, where each shared resistor pad is electrically coupled to an electrically conductive line lead, where the electrically conductive line lead carries a voltage capable of operating an electrical load. The electrical circuit can also include a load circuit portion comprising a number of unshared resistor pads. The electrical circuit can further include at least one zero ohm resistor electrically coupled to at least one shared resistor pad. The at least one zero ohm resistor can be configurable after manufacturing the printed circuit board. The load circuit portion can be electrically isolated from the line circuit portion in the absence of the at least one zero ohm resistor being further electrically coupled to at least one unshared resistor pad.

公开(公告)号：US09685494B2

公开(公告)日：2017-06-20

申请号：US14823509

申请日：2015-08-11

Applicant: Japan Display Inc.

Inventor： Kazuhiro Odaka ,  Jun Hanari ,  Toshihiro Sato

IPC: H01L23/48 ,  H01L27/32 ,  G02F1/00 ,  H05K1/11 ,  H05K3/32 ,  H05K3/36

CPC classification number: H01L27/3297 ,  G02F1/00 ,  G02F1/13452 ,  G02F2202/28 ,  H01L27/3276 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2201/10136

Abstract: A terminal is formed on a substrate. An anisotropic conductive film is disposed on the terminal. A flexible printed board is connected to the terminal via the anisotropic conductive film. At least one opening is formed in the terminal. An adhesion reinforcing portion as a projection is formed inside the opening. The adhesion reinforcing portion is formed of a material having higher adhesion to the anisotropic conductive film than a material constituting the surface of the terminal, and is adhered to the anisotropic conductive film.

公开(公告)号：US09648739B2

公开(公告)日：2017-05-09

申请号：US14558614

申请日：2014-12-02

Applicant: CANON KABUSHIKI KAISHA

Inventor： Takashi Aoki ,  Yasuhiro Sawada

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09272 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10651 ,  Y02P70/611

Abstract: An electronic component mounting structure includes a first land, a second land making a pair with the first land, an electronic component having a chip shape and including a first electrode connected to the first land and a second electrode connected to the second land, a first wiring pattern connected to the first land, and a second wiring pattern connected to the second land and including a first partial pattern overlapping a portion of a body of the electronic component in planar view, the portion being not covered with the pair of electrodes, a second partial pattern formed integral with the first partial pattern and overlapping the first electrode of the electronic component in planar view, and a third partial pattern formed integral with the second partial pattern and parallel to the first wiring pattern.

公开(公告)号：US20170072835A1

公开(公告)日：2017-03-16

申请号：US15362703

申请日：2016-11-28

Applicant: UUSI, LLC

Inventor： David W. Shank ,  John M. Washeleski ,  Edward J. Cox, II

IPC: B60Q1/00 ,  H05B33/08 ,  B60R16/02 ,  H05B37/02 ,  H05K1/14 ,  H05K7/14

CPC classification number: B60Q1/0088 ,  H01R12/62 ,  H05B33/0803 ,  H05B33/0845 ,  H05B33/0854 ,  H05B33/086 ,  H05B37/0227 ,  H05K1/02 ,  H05K1/117 ,  H05K1/14 ,  H05K1/142 ,  H05K1/16 ,  H05K2201/04 ,  H05K2201/09027 ,  H05K2201/09045 ,  H05K2201/09081 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2201/0999 ,  H05K2201/10053 ,  H05K2201/10151 ,  H05K2201/10356

Abstract: An illustrative inventory of vehicle accessory control components includes a plurality of first circuit boards and a plurality of second circuit boards. The first circuit boards each have a substrate with a plurality of circuit elements supported on the substrate. The first circuit board substrates have an overall perimeter shape including an outer edge profile and a plurality of first deviations from the outer edge profile. The second circuit boards each have a substrate with a plurality of circuit elements supported on them. The second circuit board substrates have the overall perimeter shape including the same outer edge profile as the first circuit board substrates. The second circuit board substrates include a plurality of second deviations from the outer edge profile. At least one portion of the second deviations is different than the first deviations of the first circuit boards.

Abstract translation: 车辆附件控制部件的说明性库存包括多个第一电路板和多个第二电路板。 第一电路板各自具有支撑在基板上的多个电路元件的基板。 第一电路板基板具有包括外缘轮廓和从外边缘轮廓的多个第一偏离的总体周边形状。 第二电路板各自具有支撑在它们上的多个电路元件的基板。 第二电路板基板具有包括与第一电路板基板相同的外边缘轮廓的整体周边形状。 第二电路板基板包括与外边缘轮廓的多个第二偏差。 第二偏差的至少一部分不同于第一电路板的第一偏差。

公开(公告)号：US09583810B2

公开(公告)日：2017-02-28

申请号：US14509295

申请日：2014-10-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Satoshi Ishino ,  Jun Sasaki

IPC: H01P3/02 ,  H01P3/08 ,  H05K1/02 ,  H05K1/14 ,  H01R103/00 ,  H01R12/62 ,  H01R24/50

CPC classification number: H01P3/026 ,  H01P3/08 ,  H01R12/62 ,  H01R24/50 ,  H01R2103/00 ,  H05K1/0225 ,  H05K1/0251 ,  H05K1/147 ,  H05K2201/09263 ,  H05K2201/09336 ,  H05K2201/0979 ,  H05K2201/10037 ,  H05K2201/10189

Abstract: A signal line includes a first line portion at a first layer level and a second line portion at a second layer level, which are connected by a first interlayer connection. A first ground portion at the first layer level includes end portions closer to the first line portion than an intermediate portion, and a second ground portion at the second layer level includes end portions closer to the second line portion than an intermediate portion. A second interlayer connection connects one of the end portions of the first ground portion and one of the end portions of the second ground portion. A distance between the first and second interlayer connections is less than a distance between the first line portion and the intermediate portion of the first ground portion and is less than a distance between the second line portion and the intermediate portion of the second ground portion.

Abstract translation: 信号线包括第一层级的第一线部分和第二层级的第二线部分，其通过第一层间连接连接。 第一层级的第一接地部分包括比中间部分更靠近第一线部分的端部，并且第二层级处的第二接地部分包括比中间部分更靠近第二线部分的端部。 第二层间连接将第一接地部的端部与第二接地部的端部中的一方连接。 第一和第二层间连接之间的距离小于第一线路部分和第一接地部分的中间部分之间的距离，并且小于第二线路部分和第二接地部分的中间部分之间的距离。

公开(公告)号：US09571059B2

公开(公告)日：2017-02-14

申请号：US14672138

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Jianfang Olena Zhu ,  Chung-Hao Joseph Chen ,  Ana M. Yepes

IPC: H01P5/12 ,  H03H7/38 ,  H03H7/01 ,  H05K1/02

CPC classification number: H03H7/383 ,  H03H7/0123 ,  H03H7/427 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

Abstract translation: 公开了并联通孔设计，以改善嵌入式共模扼流圈滤波器设计的阻抗匹配。 特别适用于四层印刷电路板上的这种设计，并行通孔设计有效地抑制了差分对的反射。 通过并联连接通孔，整个通孔结构的电感减小，同时电容同时增加。 通过适当选择并联通孔的数量和它们之间的间距，可以在感兴趣的频率范围内良好地控制并联通孔的阻抗。 因此，可以提高阻抗匹配，并且降低四层印刷电路板共模扼流滤波器设计的回波损耗。

公开(公告)号：US09560767B2

公开(公告)日：2017-01-31

申请号：US13734322

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoon Kim ,  Seung Hwan Kim ,  Heeseok Lee

IPC: H05K1/16 ,  H05K1/18 ,  H01L49/02 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K3/4608 ,  H05K2201/0979 ,  H05K2201/10015

Abstract: A wiring board includes a metal core including a first surface and a second surface facing each other and a first portion and a second portion disposed on the first and second surfaces, respectively. The first and second portions each include a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner. At least one capacitor is disposed in at least one interior region. The at least one capacitor includes first and second electrodes. The at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core and at least one first via electrically connects one of the wiring layers of the first portion with the first and second electrodes.

Abstract translation: 布线板包括金属芯，该金属芯包括彼此面对的第一表面和第二表面，以及分别设置在第一表面和第二表面上的第一部分和第二部分。 第一和第二部分各自包括交替堆叠的多个绝缘层和多个布线层。 至少一个电容器设置在至少一个内部区域中。 所述至少一个电容器包括第一和第二电极。 所述至少一个内部区域暴露所述金属芯的一部分，并且所述第一和第二部分中的至少一个的一部分与所述金属芯相邻，并且至少一个第一通孔将所述第一部分的所述布线层中的一个与 第一和第二电极。

公开(公告)号：US09538589B2

公开(公告)日：2017-01-03

申请号：US14168036

申请日：2014-01-30

Applicant: UUSI, LLC

Inventor： David W. Shank ,  John M. Washeleski ,  Edward J. Cox, II

IPC: B60Q1/14 ,  H05B33/08 ,  H05K1/02 ,  H05K1/14 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05B33/0803 ,  H05B33/086 ,  H05K1/02 ,  H05K1/117 ,  H05K1/142 ,  H05K1/16 ,  H05K2201/09027 ,  H05K2201/09045 ,  H05K2201/09081 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2201/0999 ,  H05K2201/10053 ,  H05K2201/10356

Abstract: An illustrative inventory of vehicle accessory control components includes a plurality of first circuit boards and a plurality of second circuit boards. The first circuit boards each have a substrate with a plurality of circuit elements supported on the substrate. The first circuit board substrates have an overall perimeter shape including an outer edge profile and a plurality of first deviations from the outer edge profile. The second circuit boards each have a substrate with a plurality of circuit elements supported on them. The second circuit board substrates have the overall perimeter shape including the same outer edge profile as the first circuit board substrates. The second circuit board substrates include a plurality of second deviations from the outer edge profile. At least one portion of the second deviations is different than the first deviations of the first circuit boards.

Abstract translation: 车辆附件控制部件的说明性库存包括多个第一电路板和多个第二电路板。 第一电路板各自具有支撑在基板上的多个电路元件的基板。 第一电路板基板具有包括外缘轮廓和从外边缘轮廓的多个第一偏离的总体周边形状。 第二电路板各自具有支撑在它们上的多个电路元件的基板。 第二电路板基板具有包括与第一电路板基板相同的外边缘轮廓的整体周边形状。 第二电路板基板包括与外边缘轮廓的多个第二偏差。 第二偏差的至少一部分不同于第一电路板的第一偏差。