公开(公告)号：US20060028222A1

公开(公告)日：2006-02-09

申请号：US11243702

申请日：2005-10-05

Applicant: Warren Farnworth ,  Salman Akram

Inventor： Warren Farnworth ,  Salman Akram

IPC: G01R31/02

CPC classification number: H05K3/326 ,  G01R1/0466 ,  G01R31/2853 ,  H05K1/118 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09081 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract translation: 用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。 每个接触件包括一个凹部和悬在该凹部上的引线图案，其构造成电接合凸起的触点。 引线适于在凹部内在z方向上移动以适应凸起接触件的高度和平面度的变化。 此外，引线可以包括用于穿透凸起的触点的突起，用于防止与凸起的触点接合的非结合外层以及与凸起的触点的形状相匹配的弯曲形状。 可以通过在基板上形成图案化的金属层，通过将聚合物基板与其上的引线附接到基板上，或者蚀刻基板以形成导电梁来形成引线。

公开(公告)号：US20050139972A1

公开(公告)日：2005-06-30

申请号：US10746745

申请日：2003-12-24

Applicant: Anthony Chiu ,  Tong Tee

Inventor： Anthony Chiu ,  Tong Tee

IPC: H01L23/50 ,  H01L23/31 ,  H01L23/495 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L21/4821 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2924/00014 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2224/45099

Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

Abstract translation: 公开了一种用于提高集成电路封装中的焊点可靠性的系统和方法。 四边形，平坦的，非引线的集成电路封装的每个端子形成有在端子的底表面中限定焊料槽的部分。 集成电路封装的管芯焊盘的外表面也形成有在管芯焊盘的周边上限定多个焊料槽的部分。 当焊料施加到管芯焊盘和端子时，填充焊料槽的焊料增加了集成电路封装的焊点可靠性。

公开(公告)号：US06700070B1

公开(公告)日：2004-03-02

申请号：US09705369

申请日：2000-11-03

Applicant: Stephen V. R. Hellriegel ,  Alexander I. Yatskov

Inventor： Stephen V. R. Hellriegel ,  Alexander I. Yatskov

IPC: H05K100

CPC classification number: H05K1/0266 ,  H05K1/0269 ,  H05K1/0393 ,  H05K3/0008 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/243 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/166 ,  H05K2203/167

Abstract: The field of the manufacture of electronic components, specifically to manufacturing flexible conductive strips having contact pads thereon, wherein a first set of alignment marks are provided on a substrate. Using the first set of alignment marks, several electronic components are formed in selected positions on the substrate. The electronic components may be formed in various groups, with a first group being formed using a first mask then, subsequent groups being formed using subsequent masks. Each of the respective masks are aligned with the first set of alignment marks in order to position the electronic components formed using the masks at the desired locations on the substrate. A second set of alignment marks are produced using the same mask as a set of electronic components that are located on the substrate. Subsequently, when a different set of features is produced, it is positioned using the second set of alignment marks located on the individual parts. Thus, tolerances can be achieved that would normally be possible only in the manufacture of individual parts, while still obtaining the advantages of the economies of scale possible by making many parts on a large sheet.

Abstract translation: 电子部件的制造领域，特别是制造其上具有接触焊盘的柔性导电条，其中第一组对准标记设置在基板上。 使用第一组对准标记，在基板上的选定位置形成几个电子部件。 电子部件可以形成为各种组，第一组使用第一掩模形成，然后使用后续掩模形成随后的组。 各个掩模中的每一个对准第一组对准标记，以便将使用掩模形成的电子部件定位在基板上的所需位置。第二组对准标记使用与一组电子装置相同的掩模 位于基板上的部件。 随后，当产生不同的特征集合时，使用位于各个部件上的第二组对准标记进行定位。 因此，可以实现通常仅在制造单个零件时可以实现的公差，同时通过在许多部件上制作大尺寸片而获得规模经济的优点。

公开(公告)号：US06686758B1

公开(公告)日：2004-02-03

申请号：US09534822

申请日：2000-03-23

Applicant: Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

Inventor： Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

IPC: G01R3102

CPC classification number: G01R1/07314 ,  H01L2924/00013 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10S438/978 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2224/29099

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract translation: 一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组， 半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。 公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

公开(公告)号：US20040011856A1

公开(公告)日：2004-01-22

申请号：US10344015

申请日：2003-07-21

Inventor： Kuno Wolf ,  Alexander Wallrauch ,  Horst Meinders ,  Barbara Will ,  Peter Urbach

IPC: B23K031/02

CPC classification number: H05K3/341 ,  B23K1/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/83101 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01R43/0235 ,  H05K2201/0373 ,  H05K2201/10924 ,  H05K2201/10969 ,  H05K2201/2036 ,  H05K2203/0405 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method is proposed for fastening at least one electrical component to a substrate using solder, in which elevations are produced in the solder substrate, the elevations being at least as high as the thickness of a solder layer to be produced, in a further step the solder, especially a solder foil, is laid upon the elevations, and in a further step, the elevations are pressed down until they have reached approximately the height of the solder, so that a soldering procedure may follow. The method is used for producing exactly specified thicknesses of solder layers having tolerances less than 10 micrometer.

Abstract translation: 提出了一种用于使用焊料将至少一个电气部件固定到基板的方法，其中在焊料基板中产生高度，其高度至少等于待生产的焊料层的厚度，在另外的步骤中， 焊料，特别是焊锡箔放置在高度上，并且在另外的步骤中，将高度压下直到它们已经达到焊料的高度，从而可以遵循焊接过程。 该方法用于制造具有小于10微米的公差的精确规定的焊料层厚度。

公开(公告)号：US20040007376A1

公开(公告)日：2004-01-15

申请号：US10193570

申请日：2002-07-09

Inventor： Eric Urdahl ,  Bruce Lee

IPC: H02G003/08

CPC classification number: H05K1/0209 ,  H05K1/0206 ,  H05K1/111 ,  H05K3/027 ,  H05K3/22 ,  H05K2201/0373 ,  H05K2201/09781 ,  H05K2203/0369 ,  Y02P70/611

Abstract: Improved thermal conductivity in printed wiring boards can be achieved without resorting to the use of dedicated thermally conductive components such as thermal vias and heat sinks. Instead, electrically functional vias, through holes, pads, and traces are modified to improve their thermal conductivity. Such modifications include thickly plating the walls of through holes or vias, possibly to the point where the via or through hole is completely filled, and also include de-planarazing the surfaces of pads and traces.

Abstract translation: 印刷电路板的热导率可以提高，而不需要使用专用导热部件，如热通孔和散热片。 相反，电功能通孔，通孔，焊盘和迹线被修改以改善其导热性。 这样的修改包括通孔或通孔的厚度电镀，可能到通孔或通孔完全填充的点，还包括对焊盘和迹线的表面进行去平面化。

公开(公告)号：US06641406B1

公开(公告)日：2003-11-04

申请号：US09705368

申请日：2000-11-03

Applicant: Alexander I. Yatskov ,  Stephen V. R. Hellriegel

Inventor： Alexander I. Yatskov ,  Stephen V. R. Hellriegel

IPC: H01R1200

CPC classification number: H01R12/62 ,  H05K1/11 ,  H05K3/243 ,  H05K3/28 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0949

Abstract: The flexible connector for high density circuit applications comprises a multilayer flexible substrate upon which are formed a plurality of contact pads, in a density required by a particular application. This density may exceed two hundred contact pads per square inch. Contact pads of similar size and configuration are formed on the surface of another device, i.e., circuit board, and provision made to align the contact pads of the connector with those of the circuit board. Micro-pads are formed on the surface of the contact pads on the connector such, that when the connector is brought into contact with the circuit board, and sufficient pressure is applied, the micro-pads make actual electrical contact with the pads of the circuit board. Since the total surface area in contact, namely the sum of the surface areas of the micro-pads, is a small fraction of the total area of the connector, a large pressure is provided at the electrical contact interface even when low pressure is provided to the connector as a whole.

Abstract translation: 用于高密度电路应用的柔性连接器包括多层柔性基板，其上形成有特定应用所需的密度的多个接触焊盘。 该密度可能超过每平方英寸200个接触垫。 具有相似尺寸和构造的接触垫形成在另一装置即电路板的表面上，并且使连接器的接触垫与电路板的接触垫对齐。 微焊盘形成在连接器上的接触焊盘的表面上，即当连接器与电路板接触并施加足够的压力时，微焊盘与电路板的实际电接触 板。 由于接触的总表面积，即微焊盘的表面积的总和，是连接器总面积的一小部分，所以即使在提供低压时也在电接触界面处提供大的压力 连接器作为一个整体。

公开(公告)号：US06621373B1

公开(公告)日：2003-09-16

申请号：US09579776

申请日：2000-05-26

Applicant: Donald R. Mullen ,  Donald V. Perino ,  Haw-Jyh Liaw

Inventor： Donald R. Mullen ,  Donald V. Perino ,  Haw-Jyh Liaw

IPC: H01P123

CPC classification number: H01P3/081 ,  H01P1/227 ,  H01P3/082 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/0116 ,  H05K2201/0323 ,  H05K2201/0373 ,  H05K2201/0715 ,  H05K2201/093

Abstract: An electronic device includes a standard dielectric material and a lossy material integrated with the standard dielectric material to selectively control the distributed resistance of the standard dielectric material. The lossy material may be inserted into the standard dielectric material. The inserted material may be resistive particles, carbon particles, open cell conductive foam, carbon impregnated open cell conductive foam, and the like. The lossy material may also be a loss inducing physical structure attached to the standard dielectric material. The loss inducing physical structure may be a planar resistive layer attached to the standard dielectric material. The planar resistive layer may have an extended surface to attenuate high frequency signals.

Abstract translation: 电子设备包括标准介电材料和与标准电介质材料集成的有损材料，以选择性地控制标准介电材料的分布电阻。 有损材料可插入到标准电介质材料中。 插入的材料可以是电阻性颗粒，碳颗粒，开孔电池导电泡沫，碳浸渍的开孔电池导电泡沫等。 损耗材料也可以是连接到标准电介质材料的损耗诱导物理结构。 损耗诱导物理结构可以是连接到标准电介质材料的平面电阻层。 平面电阻层可以具有扩展表面以衰减高频信号。

公开(公告)号：US06527563B2

公开(公告)日：2003-03-04

申请号：US09912111

申请日：2001-07-23

Applicant: Gary A. Clayton

Inventor： Gary A. Clayton

IPC: H01R1200

CPC classification number: H01R13/2414 ,  G01R1/0466 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/027 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A grid interposer for testing electrical circuits and a method of making a grid interposer. The grid interposer includes upper and lower conductive surfaces sandwiched on either side of an insulating later, connected to each other by a plurality of vias filled with conductive material. The conductive surfaces are flat topped, and incised with a grid of flat topped peaks which are small enough to cut through oxidation of electrical contacts, and ensure good electrical contact with a variety of electrode shapes.

公开(公告)号：US20030016117A1

公开(公告)日：2003-01-23

申请号：US10150579

申请日：2002-05-17

Applicant: Shipley Company, L.L.C.

Inventor： David D. Senk ,  John Schemenaur ,  Wen-Yi Lin ,  Andrew T. Hunt

IPC: H01C001/012

CPC classification number: H05K1/167 ,  H01C7/006 ,  H01C17/08 ,  H01C17/24 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2203/171

Abstract: Resistive materials having resistivities that are axis dependent are provided. Such resistive materials having a resistivity in a first direction and a very different resistivity in an orthogonal direction. These resistive materials are particularly suitable for use as resistors embedded in printed wiring boards.

Abstract translation: 提供了具有轴依赖性的电阻率的电阻材料。 这种电阻材料在正交方向具有第一方向的电阻率和非常不同的电阻率。 这些电阻材料特别适用于嵌入印刷电路板的电阻器。