中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

2340 records (took 0.032 seconds)

    WIRING BOARD
    142.
    发明申请
    WIRING BOARD 审中-公开
    接线板

    公开(公告)号：US20140118977A1

    公开(公告)日：2014-05-01

    申请号：US14147611

    申请日：2014-01-06

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Satoshi ITO ,  Yoichi MORIYA ,  Tetsuo KANAMORI ,  Yukihiro YAGI ,  Yuki YAMAMOTO

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/188 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/10378 ,  H05K2203/0323 ,  H05K2203/0369 ,  H05K2203/0376 ,  H01L2924/00

    Abstract: A wiring board includes an insulating layer, and an upper wiring pattern and a lower wiring pattern arranged with the insulating layer interposed therebetween. A truncated cone-shaped projection is integral with the lower wiring pattern so as to project at the upper wiring pattern side, and a truncated cone-shaped projection is integral with the upper wiring pattern so as to project at the lower wiring pattern side. Bonding end portions of the projections are bonded to each other to form an inter-layer connection conductor. The inter-layer connection conductor conducts the upper wiring pattern and the lower wiring pattern.

    Abstract translation: 布线板包括绝缘层，以及布置有绝缘层的上布线图案和下布线图案。 截头圆锥形突起与下布线图形成一体，以便在上布线图案侧突出，并且截顶锥形突起与上布线图形成一体，以便在下布线图案侧突出。 突起的接合端部彼此接合以形成层间连接导体。 层间连接导体导通上布线图案和下布线图案。

    Interposer having a defined through via pattern
    143.
    发明授权
    Interposer having a defined through via pattern 有权
    内插器具有定义的通孔图案

    公开(公告)号：US08664768B2

    公开(公告)日：2014-03-04

    申请号：US13463474

    申请日：2012-05-03

    Applicant: Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

    Inventor： Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/053 ,  H01L23/12

    CPC classification number: H01L23/485 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/115 ,  H05K2201/068 ,  H05K2201/09781 ,  H05K2201/10378

    Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

    Abstract translation: 一种结构包括具有多个球的衬底，半导体芯片和电连接衬底和半导体芯片的插入器。 所述插入器包括第一侧，与所述第一侧相对的第二侧，至少一个第一排除区域，所述至少一个第一排除区域延伸穿过所述多个球的每个球上方的所述插入器，至少一个主动通孔，其从所述插入件的第一侧延伸到 其中所述至少一个活性通孔形成在所述至少一个第一排除区域的外部，并且其中在所述至少一个第一排除区域内没有形成活性通孔，以及至少一个虚拟通孔， 所述插入器的第一侧到所述插入件的第二侧，其中所述至少一个虚拟通孔形成在所述至少一个第一排除区域内。

    COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET
    145.
    发明申请
    COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET 有权
    合格的核心外围导线半导体插座

    公开(公告)号：US20140043782A1

    公开(公告)日：2014-02-13

    申请号：US14058863

    申请日：2013-10-21

    Applicant: HSIO TECHNOLOGIES, LLC

    Inventor： James Rathburn

    IPC: H01L23/522 ,  H05K3/40

    CPC classification number: H01L23/34 ,  G01R1/0416 ,  H01L23/522 ,  H01L2224/13 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/10378 ,  H05K2203/162 ,  Y10T29/49165

    Abstract: An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.

    Abstract translation: IC器件上的端子和印刷电路板（PCB）上的接触焊盘之间的电气互连。 电互连包括具有第一表面的基板，该第一表面具有多个开口，其布置成对应于IC器件上的端子。 柔性材料位于开口中。 多个第一导电迹线沿着衬底的第一表面延伸到柔性材料上。 柔性材料提供抵抗第一导电迹线弯曲到开口中的偏压力。 延伸穿过衬底的通孔电耦合第一导电迹线。 多个第二导电迹线沿着衬底的第二表面延伸并且电耦合到通孔。 第二导电迹线被配置为与PCB上的接触焊盘电耦合。

Patent Agency Ranking