公开(公告)号：US20150072175A1

公开(公告)日：2015-03-12

申请号：US14230925

申请日：2014-03-31

Applicant: Johnson Controls Technology Company

Inventor： Richard M. DeKeuster ,  Robert J. Mack ,  Edward J. Soleski ,  Matthew R. Tyler ,  Stephen D. Cash ,  Mikhail S. Balk

IPC: H01M2/12

CPC classification number: H01M2/22 ,  B60L1/003 ,  B60L1/02 ,  B60L1/14 ,  B60L3/0046 ,  B60L3/12 ,  B60L11/123 ,  B60L11/14 ,  B60L11/1803 ,  B60L11/1851 ,  B60L11/1861 ,  B60L11/1864 ,  B60L11/1874 ,  B60L11/1877 ,  B60L11/1879 ,  B60L15/20 ,  B60L2210/10 ,  B60L2210/40 ,  B60L2240/34 ,  B60L2240/545 ,  B60L2240/547 ,  B60L2240/549 ,  B60L2250/10 ,  B60L2260/26 ,  B60L2270/20 ,  B60R16/03 ,  B60R16/033 ,  G01R31/025 ,  G01R31/362 ,  G01R31/3627 ,  H01H47/325 ,  H01M2/1077 ,  H01M2/1205 ,  H01M2/1211 ,  H01M2/1252 ,  H01M2/20 ,  H01M2/206 ,  H01M2/24 ,  H01M2/305 ,  H01M2/32 ,  H01M2/34 ,  H01M2/342 ,  H01M4/661 ,  H01M4/665 ,  H01M10/04 ,  H01M10/0413 ,  H01M10/058 ,  H01M10/425 ,  H01M10/4257 ,  H01M10/482 ,  H01M10/486 ,  H01M10/6551 ,  H01M2010/4271 ,  H01M2010/4278 ,  H01M2200/103 ,  H01M2220/20 ,  H01M2250/20 ,  H01R12/716 ,  H02H7/18 ,  H02J7/0021 ,  H02J7/0063 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/18 ,  H05K3/32 ,  H05K2201/10492 ,  H05K2201/1053 ,  H05K2201/10545 ,  Y02T10/6217 ,  Y02T10/645 ,  Y02T10/7005 ,  Y02T10/7011 ,  Y02T10/7016 ,  Y02T10/7022 ,  Y02T10/7044 ,  Y02T10/705 ,  Y02T10/7061 ,  Y02T10/7077 ,  Y02T10/7216 ,  Y02T10/7241 ,  Y02T10/7275 ,  Y10T29/49108 ,  Y10T29/4911 ,  Y10T29/49114

Abstract: Present embodiments are directed to a battery module including a venting assembly and a method of manufacturing the battery module. The venting assembly may, in certain embodiments, be designed to vent gases from a plurality of battery cells disposed in a housing of the battery module. Each of the plurality of battery cells may include a battery cell vent. The venting assembly may include a lid designed to be coupled to the housing and disposed over the battery cells in the housing. In some embodiments, the lid includes a vent chamber formed in the lid and designed to receive and direct gases vented from the plurality of battery cells away from the battery module.

Abstract translation: 本实施例涉及一种电池模块，其包括通气组件和制造电池模块的方法。 在某些实施例中，排气组件可被设计成从设置在电池模块的壳体中的多个电池单元排出气体。 多个电池单元中的每一个可以包括电池单元排气口。 排气组件可以包括设计成联接到壳体并设置在壳体中的电池单元上的盖。 在一些实施例中，盖包括形成在盖中并被设计成接收和引导从多个电池单元排出的气体远离电池模块的排气室。

公开(公告)号：US20150049443A1

公开(公告)日：2015-02-19

申请号：US13965246

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg

IPC: H05K1/18

CPC classification number: H05K1/189 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/5383 ,  H01L23/5387 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/0209 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/145 ,  H05K3/32 ,  H05K3/361 ,  H05K2201/05 ,  H05K2201/10378 ,  H05K2201/105 ,  H05K2201/1053 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10954 ,  H05K2201/10962 ,  H01L2924/00

Abstract: According to various embodiments, a chip arrangement may be provided, the chip arrangement may include: a first carrier; at least one chip arranged over the first carrier; a flexible structure including a wiring layer structure; and a contact structure arranged between the first carrier and the wiring layer structure, wherein the at least one chip is electrically coupled to the first carrier via the wiring layer structure and the contact structure.

Abstract translation: 根据各种实施例，可以提供芯片布置，芯片布置可以包括：第一载体; 布置在所述第一载体上的至少一个芯片; 包括布线层结构的柔性结构; 以及布置在所述第一载体和所述布线层结构之间的接触结构，其中所述至少一个芯片经由所述布线层结构和所述接触结构电耦合到所述第一载体。

公开(公告)号：US08913398B2

公开(公告)日：2014-12-16

申请号：US14016707

申请日：2013-09-03

Applicant: Shinji Watanabe ,  Nobuhiro Mikami ,  Junya Sato ,  Kenichiro Fujii ,  Katsumi Abe ,  Atsumasa Sawada

Inventor： Shinji Watanabe ,  Nobuhiro Mikami ,  Junya Sato ,  Kenichiro Fujii ,  Katsumi Abe ,  Atsumasa Sawada

IPC: H05K7/00 ,  H05K3/00 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H05K3/32

CPC classification number: H05K1/18 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1515 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0271 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/32 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09436 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  H05K2203/302 ,  Y02P70/611 ,  H01L2924/00

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract translation: 本发明的目的在于，当将半导体封装安装在弯曲的基板上时，可以抑制对半导体封装件施加的应力。 在安装基板1中，将半导体封装20安装在其至少一部分上包括弯曲表面的弯曲板10上。 弯曲板10包括设置在半导体封装20安装的弯曲表面部分的区域上并具有平坦的上表面的基座部分13a和设置在基座部分的平坦表面上的多个焊盘部分15a 13a。 基座部分13a由绝缘材料形成。 半导体封装20安装在焊盘部分15a上。

公开(公告)号：US08908387B2

公开(公告)日：2014-12-09

申请号：US13562683

申请日：2012-07-31

Applicant: Yukinobu Mikado ,  Shunsuke Sakai ,  Takashi Kariya ,  Toshiki Furutani

Inventor： Yukinobu Mikado ,  Shunsuke Sakai ,  Takashi Kariya ,  Toshiki Furutani

IPC: H05K7/12 ,  H05K1/18 ,  H05K3/30 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/185 ,  H01G2/06 ,  H05K1/0207 ,  H05K1/115 ,  H05K3/30 ,  H05K3/32 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49146

Abstract: A wiring board includes a substrate having an opening portion, electronic components positioned in the opening portion of the substrate and including first and second electronic components, and an insulation layer formed over the substrate and the first and second components. The first component has first and second electrodes having side portions on side surfaces of the first component, the second component has first and second electrodes having side portions on side surfaces of the second component, the first electrode of the first component and the first electrode of the second component are set to have substantially the same electric potential, and the first component and the second component are positioned in the opening portion of the substrate such that the side portion of the first electrode of the first component is beside the side portion of the first electrode of the second component.

Abstract translation: 布线板包括具有开口部分的基板，位于基板的开口部分中的电子部件，并且包括第一和第二电子部件，以及形成在基板和第一和第二部件上的绝缘层。 第一部件具有在第一部件的侧面具有侧部的第一电极和第二电极，第二部件具有第一部件和第二电极，第一部件的第一电极和第二电极具有在第二部件的侧面上的侧面部分，第一部件的第一电极和第一部件的第一电极 第二部件被设定为具有大致相同的电位，并且第一部件和第二部件位于基板的开口部分中，使得第一部件的第一电极的侧部位于第二部件的侧部 第二部件的第一电极。

公开(公告)号：US20140268592A1

公开(公告)日：2014-09-18

申请号：US14211127

申请日：2014-03-14

Applicant: Indiana Integrated Circuits, LLC

Inventor： Jason M. Kulick ,  Tian Lu

IPC: H05K3/30 ,  H05K1/18

CPC classification number: H05K1/18 ,  H05K1/181 ,  H05K3/34 ,  H05K2201/1053 ,  Y02P70/611 ,  Y10T29/49128

Abstract: Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.

Abstract translation: 与微芯片组装和处理领域相关的装置和方法，特别是用于组装和处理由固体边缘到边缘互连制成的微芯片的装置和方法，例如QuiltPackaging®互连技术。 专门的组装工具被配置为拾取一个或多个微芯片，将微芯片放置在与衬底，封装或另一微芯片对准的指定位置，并且通过包括回流焊在内的各种方法之一促进电接触。 这种专门的组装工具执行加热功能以回流焊料以在多个微芯片之间建立电和机械互连。 另外，互连的微芯片可以布置成任意大的阵列。

公开(公告)号：US08836136B2

公开(公告)日：2014-09-16

申请号：US13405108

申请日：2012-02-24

Applicant: Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang ,  Zhijun Zhao

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang ,  Zhijun Zhao

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/8518 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49149 ,  Y10T29/49151 ,  H01L2224/45664 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

Abstract translation: 微电子封装可以包括引线键合，其具有结合到衬底上的相应导电元件的底部并且与基底相对的端部。 从衬底延伸的电介质封装层覆盖引线接合的部分，使得引线键合的被覆部分通过封装层彼此分离，其中引线键合的未封装部分由未被覆盖的引线键的部分限定 通过封装层。 未封装的部分可以布置在具有最小间距的图案的位置处，该最小间距大于相邻引线键的基部之间的第一最小间距。

公开(公告)号：US20140252541A1

公开(公告)日：2014-09-11

申请号：US13792293

申请日：2013-03-11

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Ivan Dimitrov Nanov ,  John Frank Steel

IPC: H01L23/34 ,  H05K3/32

CPC classification number: H05K3/32 ,  H01L23/36 ,  H01L23/49555 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/1003 ,  H05K2201/10166 ,  H05K2201/1053 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A power train assembly is provided. The power train assembly includes a component package including a first transistor having a first gate, a first drain, and a first source, a second transistor having a second gate, a second drain, and a second source, and a thermal pad configured to dissipate heat generated in the component package, wherein the thermal pad is electrically coupled to the first source and the second drain. The power train assembly further includes a printed circuit board (PCB) electrically coupled to the component package, and an electrical component electrically coupled directly to the thermal pad, wherein the electrical component is external to the component package.

Abstract translation: 提供动力总成组件。 动力传动系组件包括部件封装，其包括具有第一栅极，第一漏极和第一源极的第一晶体管，具有第二栅极，第二漏极和第二源极的第二晶体管，以及散热板 在组件封装中产生的热量，其中散热垫电耦合到第一源极和第二漏极。 动力传动系组件还包括电耦合到部件封装的印刷电路板（PCB），以及直接耦合到散热焊盘的电气部件，其中电组件在组件封装外部。

公开(公告)号：US20140183267A1

公开(公告)日：2014-07-03

申请号：US13974165

申请日：2013-08-23

Applicant: Hon Hai Precision Industry Co., Ltd. ,  Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.

Inventor： ZONG-YUAN SUN ,  DA-HUA XIAO

IPC: G06K19/077

CPC classification number: G06K19/07758 ,  G05B19/4183 ,  H05K1/0266 ,  H05K1/181 ,  H05K2201/10098 ,  H05K2201/1053

Abstract: A printed circuit board (PCB) includes a base board, a number of electronic components and at least one radio frequency identification (RFID) tag. The electronic components are mounted on the base board. The at least one RFID tag is attached to one or more of the electronic components, and is programmed with identification information of the PCB.

Abstract translation: 印刷电路板（PCB）包括基板，多个电子部件和至少一个射频识别（RFID）标签。 电子部件安装在基板上。 至少一个RFID标签被附接到一个或多个电子部件，并且被编程为PCB的识别信息。

公开(公告)号：US20140111958A1

公开(公告)日：2014-04-24

申请号：US13956293

申请日：2013-07-31

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jae Soo Lee

IPC: H05K7/02 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K3/4697 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49139 ,  Y10T29/49142

Abstract: The present invention relates to a substrate structure having electronic components and a method of manufacturing a substrate structure having electronic components and can reduce signal loss and internal resistance and improve process efficiency by bringing a first terminal of a first electronic component and a second terminal of a second electronic component in direct contact with each other or in direct contact with each other by solder to minimize a path between the electronic components.

Abstract translation: 本发明涉及具有电子部件的基板结构体和具有电子部件的基板结构体的制造方法，能够通过将第一电子部件的第一端子和第二端子的第二端子 第二电子部件彼此直接接触或通过焊料彼此直接接触，以使电子部件之间的路径最小化。

公开(公告)号：US08659135B2

公开(公告)日：2014-02-25

申请号：US11572873

申请日：2005-07-21

Applicant: Michael Bauer ,  Ulrich Bachmaier ,  Robert-Christian Hagen ,  Jens Pohl ,  Rainer Steiner ,  Hermann Vllsmeler ,  Holger Woerner ,  Bernhard Zuhr

Inventor： Michael Bauer ,  Ulrich Bachmaier ,  Robert-Christian Hagen ,  Jens Pohl ,  Rainer Steiner ,  Hermann Vllsmeler ,  Holger Woerner ,  Bernhard Zuhr

IPC: H01L23/488

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2201/10924 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor stack and a semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack is disclosed. In one embodiment, a semiconductor chip is arranged between the intermediate wiring board and the wiring substrate, which is electrically connected by way of the wiring substrate on the one hand to external contacts on the underside of the wiring substrate and on the other hand to contact terminal areas in the edge regions of the wiring substrate. The intermediate wiring board has angled-away external flat conductors, which are electrically connected in the contact terminal areas of the wiring board. Furthermore, on the upper side of the intermediate wiring board, arranged on the free ends of the internal flat conductors are external contact terminal areas, which correspond in size and arrangement to external contacts of a semiconductor device to be stacked.

Abstract translation: 公开了一种具有布线基板和半导体器件堆叠的中间布线板的半导体堆叠和半导体基底器件。 在一个实施例中，半导体芯片布置在中间布线板和布线基板之间，其一方面通过布线基板与布线基板的下侧上的外部触点电连接，另一方面与布线基板 接线基板的边缘区域的端子区域。 中间布线板具有成角度的外部扁平导体，其电连接在布线板的接触端子区域中。 此外，在中间布线板的上侧，布置在内部扁平导体的自由端上的是外部接触端子区域，其尺寸和布置对应于要堆叠的半导体器件的外部触点。