公开(公告)号：US5493074A

公开(公告)日：1996-02-20

申请号：US264781

申请日：1994-06-23

Applicant: Katsuhiro Murata ,  Mitsumasa Shibata ,  Toru Hatakeyama ,  Tadaaki Isono

Inventor： Katsuhiro Murata ,  Mitsumasa Shibata ,  Toru Hatakeyama ,  Tadaaki Isono

IPC: H01B5/14 ,  H01B13/00 ,  H01R11/00 ,  H01R43/00 ,  H05K1/00 ,  H05K3/24 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/38 ,  H05K1/09 ,  H05K1/02

CPC classification number: H05K3/28 ,  H05K3/361 ,  H05K1/0393 ,  H05K2201/09881 ,  H05K2203/0723 ,  H05K3/244 ,  H05K3/323 ,  H05K3/3473 ,  H05K3/386 ,  Y10T29/49155

Abstract: A flexible circuit board device for connecting to an electronic device comprised of a flexible circuit board made from flexible resistive film, an adhesive layer formed on the flexible resistive film, electrical conductive circuits formed on the adhesive layer and cured films filling the gaps between the conductive circuits. The electrical conductive circuits are formed of conductor metal foil and a plating film covering the surface of the conductor.

Abstract translation: 一种用于连接到由柔性电阻膜制成的柔性电路板的电子装置的柔性电路板装置，形成在柔性电阻膜上的粘合层，形成在粘合剂层上的导电电路和填充导电 电路。 导电电路由导体金属箔和覆盖导体表面的镀膜形成。

公开(公告)号：US5472546A

公开(公告)日：1995-12-05

申请号：US244641

申请日：1994-05-27

Applicant: Hartmuth F. Thaler

Inventor： Hartmuth F. Thaler

IPC: H05K3/20 ,  H05K3/38 ,  B32B31/10 ,  B32B31/18

CPC classification number: H05K3/202 ,  H05K2201/09881 ,  H05K2201/10424 ,  H05K3/386 ,  Y10T156/1056 ,  Y10T156/1062 ,  Y10T156/1077 ,  Y10T156/1089 ,  Y10T29/301 ,  Y10T29/49128

Abstract: To make a printed circuit board, bores bridge gaps between where conductor paths are to be located, and are then filled with an adhesive. The gaps between where the conductor paths are to be located then caustically removed so that a conductor path skeleton results which is held together by the adhesive bridges. Finally, the conductor path skeleton is affixed to an insulating layer.

Abstract translation: PCT No.PCT / EP93 / 02167 Sec。 371日期：1994年5月27日 102（e）日期1994年5月27日PCT提交1993年8月14日PCT公布。 公开号WO94 / 08441 日期1994年04月14日。为了制造印刷电路板，在导体路径所在的位置之间插入桥接间隙，然后用粘合剂填充。 导体路径之间的位置之间的间隙将被苛刻地去除，从而导致通过粘合剂桥固定在一起的导体路径骨架。 最后，将导体路径骨架固定在绝缘层上。

公开(公告)号：US5464725A

公开(公告)日：1995-11-07

申请号：US959752

申请日：1992-10-13

Applicant: Kiminori Ishido ,  Masahiro Yamaguchi

Inventor： Kiminori Ishido ,  Masahiro Yamaguchi

IPC: G03F7/00 ,  H05K3/06 ,  H05K3/28 ,  G03C5/00

CPC classification number: G03F7/0035 ,  H05K3/28 ,  H05K2201/09881 ,  H05K2203/058 ,  H05K2203/0582 ,  H05K2203/0759 ,  H05K3/061

Abstract: After pads 2 for mounting parts are formed at desired positions on an insulating board 1 in a circuit forming process using etching resist 3, the etching resist 3 is left on the pads without peeling it off. A first photosolder resist 4 is then formed between the pads 2, exposed to light, and developing using a solvent able to separate the etching resist 3 as a developing liquid, following which the etching resist 3 is peeled off together with the not yet fully hardened first photosolder resist 4. After formation of the first photosolder resist 4, a second photosolder resist is formed on desired areas excluding the interspaces between the pads 2, exposed to light, and developed. Consequently, when a photosolder resist is formed between pads pitched at narrow intervals on a printed wiring board, attachment of the photosolder resist to the pads due to misalignment between the insulating board and a photo-mask can be avoided.

Abstract translation: 在使用抗蚀剂3的电路形成工艺中，在绝缘板1上的期望位置处形成用于安装部件的焊盘2之后，将抗蚀剂3留在焊盘上而不剥离。 然后将第一光固化剂抗蚀剂4形成在暴露于光的焊盘2之间，并使用能够分离作为显影液的抗蚀剂3的溶剂显影，随后将抗蚀剂3与尚未完全硬化 第一光固化剂抗蚀剂4.在形成第一光致抗蚀剂4之后，在除了被曝光的衬垫2之间的间隙之外的所需区域上形成第二光固化抗蚀剂并显影。 因此，当在印刷电路板上以窄间隔形成在衬垫之间形成光阻抗剂时，可以避免由于绝缘板和光掩模之间的不对准而将光敏抗蚀剂附着到焊盘。

公开(公告)号：US5464662A

公开(公告)日：1995-11-07

申请号：US300131

申请日：1994-09-02

Applicant: Tomoo Murakami ,  Takanori Tsunoda

Inventor： Tomoo Murakami ,  Takanori Tsunoda

IPC: H05K3/24 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/28 ,  H05K3/38 ,  B05D5/12

CPC classification number: H05K3/0094 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09745 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0369 ,  H05K2203/0508 ,  H05K2203/0574 ,  H05K2203/0759 ,  H05K2203/1394 ,  H05K3/0082 ,  H05K3/061 ,  H05K3/383 ,  Y02P70/611

Abstract: A fabrication method of a printed wiring board in which the halation effect of light irradiated to a solder resist film is utilized in a process of selectively removing the solder resist film. After a conductive layer is patterned to a given circuit pattern including soldering pads, the solder resist film is formed on the base material to cover the patterned conductive layer. The solder resist film is selectively exposed to light utilizing reflection of the irradiated light from the insulating base material and developed so that the solder resist film is selectively left in areas adjacent to the respective soldering pads. Then, an etching resist film is formed to cover the patterned conductive layer except for the soldering pads, and surface areas of the respective soldering pads are selectively etched using the etching resist film as a mask to produce solder resist dams made of the solder resist film left on the base material. Solder films are formed on the respective soldering pads thus selectively etched. Electronic components can be soldered on the soldering pads with satisfactory reliability even if the soldering pads have narrow pitches such as 500 .mu.m or less.

Abstract translation: 在选择性去除阻焊膜的工序中，利用照射到阻焊膜的光的晕影效果的印刷电路板的制造方法。 在将导电层图案化为包括焊盘的给定电路图案之后，在基底材料上形成阻焊膜以覆盖图案化的导电层。 利用来自绝缘基材的照射光的反射来选择性地将阻焊膜暴露于光，并显影，使得阻焊膜选择性地留在与各个焊盘相邻的区域中。 然后，形成抗蚀剂膜以覆盖除了焊盘之外的图案化导电层，并且使用抗蚀剂膜作为掩模来选择性地蚀刻各个焊盘的表面积，以形成由阻焊膜制成的阻焊堤 留在基材上。 在相应的焊盘上形成焊接膜，从而选择性地蚀刻。 即使焊盘具有500μm以下的窄间距，也可以将电子部件焊接在焊盘上，其可靠性良好。

公开(公告)号：US5371653A

公开(公告)日：1994-12-06

申请号：US29919

申请日：1993-03-11

Applicant: Masatsugu Kametani ,  Kazuhiro Umekita

Inventor： Masatsugu Kametani ,  Kazuhiro Umekita

IPC: H05K1/11 ,  H01L23/467 ,  H01L23/538 ,  H05K1/02 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K7/20

CPC classification number: H05K1/0207 ,  H01L23/467 ,  H01L23/5383 ,  H01L23/5384 ,  H05K3/429 ,  H05K3/4641 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0201 ,  H05K1/0206 ,  H05K2201/0209 ,  H05K2201/0352 ,  H05K2201/062 ,  H05K2201/09327 ,  H05K2201/09581 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2201/10689 ,  H05K3/3447

Abstract: A circuit board includes a circuit-conductor layer, a ground layer and a power source layer superposed in a multilayer form through dielectric layers therebetween, A heat conduction through inside of the circuit board is enhanced so that circuit chips mounted on the circuit board can be cooled down to a level capable of operating normally, The circuit board can be formed to be compact, In order to enhance the heat transfer in the circuit board, at least one of the ground layer and power source layer is formed in a multilayer manner, It is preferable to form these layers at a thickness larger than that of the circuit-conductor layer, Further, preferably, the pin of the chip mounted on the board and at least one of the ground layer and power supply layer are connected to each other in such a manner as to enhance the heat conduction.

Abstract translation: 电路板包括电路导体层，接地层和电源层，通过其间的介电层叠加成多层形式。通过电路板内部的热传导增强，使得安装在电路板上的电路芯片可以 冷却到能够正常工作的水平。电路板可以形成为紧凑的。为了增强电路板中的热传递，接地层和电源层中的至少一个以多层形式形成， 优选以比电路导体层的厚度大的方式形成这些层。此外，优选地，安装在基板上的芯片的引脚和接地层和电源层中的至少一个彼此连接 以增强热传导的方式。

公开(公告)号：US5369881A

公开(公告)日：1994-12-06

申请号：US124268

申请日：1993-09-20

Applicant: Masaichi Inaba ,  Norimasa Fujita

Inventor： Masaichi Inaba ,  Norimasa Fujita

IPC: H05K3/02 ,  H05K3/00 ,  H05K3/04 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/22 ,  H05K3/24 ,  H05K3/28 ,  H05K3/38

CPC classification number: H05K3/045 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0554 ,  H05K2203/0726 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/064 ,  H05K3/107 ,  H05K3/388 ,  Y10T29/49155

Abstract: This invention provides a method of forming a circuit wiring pattern which cannot be formed by a prior art method such as etching or plating. This method comprises a step of forming trenches for forming a circuit wiring pattern at predetermined positions on at least one of the surface of an insulating base material and then filling a conductive material into the trenches, a step of removing conductor layers in such a manner that the conductor layers formed by the step described above exist only in the trenches formed in the insulating base material and gap portions of the circuit wiring pattern comprising the conductor layers formed in the trenches of the insulating base material are exposed, and a step of forming an insulating surface protection layer.

Abstract translation: 本发明提供一种形成电路布线图案的方法，该方法不能用诸如蚀刻或电镀的现有技术方法形成。 该方法包括以下步骤：在绝缘基材的至少一个表面上的预定位置处形成用于形成电路布线图案的沟槽，然后将导电材料填充到沟槽中，以如下方式除去导体层的步骤： 由上述步骤形成的导体层仅存在于形成在绝缘基材中的沟槽中，并且包含形成在绝缘基材的沟槽中的导体层的电路布线图案的间隙部分露出， 绝缘表面保护层。

公开(公告)号：US5201974A

公开(公告)日：1993-04-13

申请号：US475578

申请日：1990-02-06

Applicant: Frederick A. West

Inventor： Frederick A. West

IPC: H05K1/00 ,  H05K1/09 ,  H05K3/20 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K3/4632 ,  H05K3/20 ,  H05K3/4617 ,  H05K7/06 ,  H05K1/0393 ,  H05K1/095 ,  H05K2201/0129 ,  H05K2201/09809 ,  H05K2201/09881 ,  H05K2201/1028 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1545 ,  H05K3/1275 ,  H05K3/366 ,  H05K3/4069 ,  H05K3/4614 ,  Y10S428/901 ,  Y10T156/1015 ,  Y10T29/49126

Abstract: Patterned electrically conductive structures, such as circuit elements, in single or multiple laminar form, and their manufacture. The basic laminar structure is made by sizing a removable substrate to substantially equal depth with an electrically conductive material over a given area configured as a circuit element and with an electrically non-conductive material elsewhere, bonding the respective sizing materials in place and together, and separating the substrate to leave a lamina of electrically conductive and non-conductive materials side-by-side. Face-to-face juxtaposition of such substrate-less laminae provides built-up or laminated products.

Abstract translation: 图案化的导电结构，例如单层或多层流形式的电路元件及其制造。 基本的层状结构是通过将可移除的衬底在给定的区域上形成与导电材料基本相同的深度来制造的，该给定区域被构造为电路元件，并且在其它地方使用不导电材料，将相应的施胶材料粘合在一起，并将它们结合在一起;以及 分离衬底以并排留下导电和非导电材料层。 这种无底板的面对面并置提供积层或层压产品。

公开(公告)号：US4927742A

公开(公告)日：1990-05-22

申请号：US275358

申请日：1988-11-23

Applicant: Thomas S. Kohm

Inventor： Thomas S. Kohm

IPC: B32B15/08 ,  C08K5/00 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4661 ,  B32B15/08 ,  C08K5/0091 ,  H05K3/387 ,  H05K3/389 ,  H05K2201/0133 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09881 ,  H05K3/184 ,  H05K3/426 ,  H05K3/4644 ,  Y10S428/901

Abstract: A multilayer printed wiring board is described having (1) an inner layer conductive pattern on an organic insulating base material, (2) a poly(vinyl acetal)-phenolic resin coating containing an amine substituted organic zirconate or titanate coupling agent, (3) a dielectric insulating layer, (4) a bonding composition capable of being adhesion promoted for electroless metal deposition comprising a phenolic resin having at least two methylol groups and substantially free of methyl ether groups, a heat resistant aromatic or cyclic resin having functional groups capable of reacting with the methylol groups without the evolution of water, and (5) an outer conductive pattern, the multilayer board being capable of withstanding at least five soldering cycles of at least 255.degree. C. for 2 seconds without blistering or delamination. Processes for manufacturing the multilayer board are also described.

Abstract translation: 描述了一种多层印刷线路板，其具有（1）有机绝缘基材上的内层导电图案，（2）含有胺取代的有机锆酸酯或钛酸酯偶联剂的聚（乙烯醇缩醛） - 酚醛树脂涂料，（3） 电介质绝缘层，（4）能够进行无电金属沉积的粘合促进的粘合组合物，其包含具有至少两个羟甲基并且基本上不含甲基醚基团的酚醛树脂，具有能够 与羟甲基进行反应而不发生水分，和（5）外部导电图案，该多层板能够承受至少255℃的至少五个焊接周期，持续2秒而没有起泡或分层。 还描述了用于制造多层板的工艺。

公开(公告)号：US3775725A

公开(公告)日：1973-11-27

申请号：US3775725D

申请日：1972-01-24

Applicant: HOKURIKU ELECT IND

Inventor： ENDO I

IPC: H01C1/14 ,  H05K1/09 ,  H05K1/16 ,  H05K3/06 ,  H05K3/28 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/167 ,  H01C1/14 ,  H05K1/095 ,  H05K3/06 ,  H05K3/28 ,  H05K3/386 ,  H05K3/42 ,  H05K3/427 ,  H05K3/4664 ,  H05K2201/0323 ,  H05K2201/035 ,  H05K2201/09436 ,  H05K2201/09881 ,  H05K2203/1453

Abstract: A printed resistor comprising an insulating matrix board, copper layers printed on one side of said board by etching and having predetermined patterns, impedance layers screen-printed on the other side of said board, and conductors applied in holes formed in said board and extending through said holes for electrically connecting between selected ones of said copper layers and said impedance layers.

Abstract translation: 一种印刷电阻器，包括绝缘矩阵板，通过蚀刻印刷在所述板的一侧上并具有预定图案的铜层，屏幕印刷在所述板的另一侧上的阻抗层，以及施加在形成在所述板中并延伸穿过的孔中的导体 所述孔用于电连接所述铜层中的所选铜层和所述阻抗层。

公开(公告)号：US3202879A

公开(公告)日：1965-08-24

申请号：US22654662

申请日：1962-09-27

Applicant: IBM

Inventor： STERLING JOHN L

IPC: H05K1/11 ,  H05K3/04 ,  H05K3/20 ,  H05K3/46

CPC classification number: H05K3/4617 ,  H05K1/117 ,  H05K3/041 ,  H05K3/202 ,  H05K2201/09436 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2203/033