公开(公告)号：US20150054601A1

公开(公告)日：2015-02-26

申请号：US14537059

申请日：2014-11-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Nobuo IKEMOTO ,  Yuki WAKABAYASHI ,  Shigeru TAGO

IPC: H01P3/08 ,  H05K1/11 ,  H01P11/00 ,  H05K1/02

CPC classification number: H01P3/082 ,  H01P3/08 ,  H01P11/003 ,  H01R12/62 ,  H01R24/50 ,  H01R2103/00 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/115 ,  H05K1/118 ,  H05K1/147 ,  H05K3/0052 ,  H05K3/363 ,  H05K3/4623 ,  H05K3/4632 ,  H05K2201/07 ,  H05K2201/09154 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2201/10037 ,  H05K2201/10204 ,  Y10T29/49016

Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

Abstract translation: 在高频信号线中，第一信号线沿着第一介电元件组件延伸，第一参考接地导体沿着第一信号线延伸，第二信号线设置在第二电介质元件组件中或第二电介质元件组件上，并沿着第二信号线延伸 电介质元件组件，第二参考接地导体设置在第二电介质元件组件中或第二介质元件组件上并沿第二信号线延伸。 在第一介电元件组件的端部处的底表面的一部分和第二介电元件组件的端部处的顶表面的一部分被接合在一起，使得第一和第二介电元件组件的接合部分包括角部 。 第二信号线和第一信号线电耦合在一起。 第一和第二参考接地导体电耦合在一起。

公开(公告)号：US20140103524A1

公开(公告)日：2014-04-17

申请号：US14108960

申请日：2013-12-17

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L23/498

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。

公开(公告)号：US20130256010A1

公开(公告)日：2013-10-03

申请号：US13793618

申请日：2013-03-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Youb JUNG ,  Yang Je Lee

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4644 ,  H05K1/09 ,  H05K1/115 ,  H05K3/421 ,  H05K2201/09518 ,  H05K2201/09527

Abstract: Disclosed herein are a method of manufacturing a multilayer printed circuit board (PCB), a via which is an inner via hole (IVH) having a stable structure so as to easily form a fine pattern, thereby thinning a product, and a multilayer PCB manufactured via the same. The method includes preparing a base substrate including copper foils formed on opposite surfaces or a single surface of the base substrate; forming an insulating layer on the base substrate via a coating process; processing a via hole through the insulating layer formed on the base substrate up to the base substrate; performing fill plating on the via hole; and stacking at least one circuit layer on a metal layer that is formed via the fill plating.

Abstract translation: 本文公开了一种制造多层印刷电路板（PCB）的方法，通孔是具有稳定结构的内部通孔（IVH），以便容易地形成精细图案，从而使产品变薄，制造多层PCB 通过相同 该方法包括制备包括在相对表面上形成的铜箔或基底基板的单个表面的基底基板; 通过涂覆工艺在基底基板上形成绝缘层; 处理穿过形成在基底基板上的绝缘层直到基底的通孔; 在通孔上进行填充电镀; 并且在经由填充电镀形成的金属层上堆叠至少一个电路层。

公开(公告)号：US08530752B2

公开(公告)日：2013-09-10

申请号：US12632948

申请日：2009-12-08

Applicant: Kenichi Kawabata ,  Takaaki Morita

Inventor： Kenichi Kawabata ,  Takaaki Morita

IPC: H05K1/16

CPC classification number: H05K3/4652 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/0058 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0358 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/1105 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49128 ,  Y10T428/24917 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A multilayer circuit board comprises core layers 101 and 102 made of a core material impregnated with resin, resin layers 111 and 112 interposed between the core layers 101 and 102, a wiring pattern 140 embedded in the resin layers 111 and 112. The core layers 101 and 102 have a thickness of 100 μm or smaller, whereby the entire board can significantly be thinned. Furthermore, the less strong resin layers 111 and 112 are interposed between the hard core layers 101 and 102, whereby the entire board has increased strength.

Abstract translation: 多层电路板包括由浸渍有树脂的芯材制成的芯层101和102，插入在芯层101和102之间的树脂层111和112，嵌入在树脂层111和112中的布线图案140.芯层101 102的厚度为100μm以下，从而能够使整个基板变薄。 此外，较不强的树脂层111和112插入在硬芯层101和102之间，由此整个板具有增加的强度。

公开(公告)号：US08373069B2

公开(公告)日：2013-02-12

申请号：US12647015

申请日：2009-12-24

Applicant: Takashi Kariya ,  Daiki Komatsu

Inventor： Takashi Kariya ,  Daiki Komatsu

IPC: H05K1/03

CPC classification number: H05K1/162 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/108 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T29/4916 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.

Abstract translation: 一种电子部件安装基板，包括由具有第一表面和第二表面的树脂制成的支撑层，在所述支撑层的第一表面上的有机绝缘层，在所述支撑层的第一表面的相对侧上具有第一表面， 与支撑层的第一表面接触，有机层的第一表面上的无机绝缘层，支撑层的第二表面上的导体和在有机层的第二表面上的第一导电电路。 无机层具有第二导电电路和用于将电子部件安装在无机层内部的焊盘。 有机层在有机层内部具有通孔导体并连接第一和第二电路。 支撑层在支撑层内部具有导电柱并连接第一电路和导体。

公开(公告)号：US20120043128A1

公开(公告)日：2012-02-23

申请号：US13064657

申请日：2011-04-06

Applicant: Kyoung Ro Yoon ,  Joung Gul Ryu ,  Young Hwan Shin

Inventor： Kyoung Ro Yoon ,  Joung Gul Ryu ,  Young Hwan Shin

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K3/429 ,  H05K2201/09454 ,  H05K2201/09527 ,  H05K2203/1572 ,  Y10T29/49165

Abstract: The present invention provides a multilayer printed circuit board and a method for manufacturing the same. The printed circuit board includes: an inner circuit layer which is disposed on a first insulating layer; a via land which is disposed on the first insulating layer to be spaced apart from the inner circuit layer and has a hole; a second insulating layer which is disposed on the first insulating layer including the inner circuit layer and the via land; first and second outer circuit layers which are disposed on outer surfaces of the first and second insulating layers, respectively; and a via which passes through the hole of the via land and the first and second insulating layers and electrically interconnects the first and second outer circuit layers.

Abstract translation: 本发明提供一种多层印刷电路板及其制造方法。 印刷电路板包括：设置在第一绝缘层上的内部电路层; 通孔焊盘，其设置在所述第一绝缘层上以与所述内部电路层间隔开并具有孔; 第二绝缘层，其设置在包括内部电路层和通路接地的第一绝缘层上; 第一和第二外部电路层，分别设置在第一和第二绝缘层的外表面上; 以及通孔，其通过通孔接合区的孔和第一和第二绝缘层，并使第一和第二外部电路层电连接。

公开(公告)号：US20120011716A1

公开(公告)日：2012-01-19

申请号：US13137695

申请日：2011-09-02

Applicant: Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

Inventor： Han Kim ,  Mi Sun Hwang ,  Suk Won Lee ,  Chang Gun Oh

IPC: H05K3/42

CPC classification number: H05K3/462 ,  H05K1/0265 ,  H05K1/0366 ,  H05K3/025 ,  H05K3/108 ,  H05K3/4623 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board including: preparing a first double-sided substrate including a first insulating layer, a first lower copper layer, a second circuit layer including a first lower land, and a first via; preparing a second double-sided substrate including a second insulating layer, a third lower copper layer, a fourth circuit layer including a second lower land, and a second via; disposing a third insulating layer between the second circuit layer and the fourth circuit layer such that the first lower land and the second lower land are electrically connected to each other though a conductive bump; and forming a first circuit layer including a first circuit pattern connected to the first via on the first lower copper layer and forming a third circuit layer including a third circuit pattern connected to the second via on the third lower copper layer.

Abstract translation: 一种制造印刷电路板的方法，包括：制备包括第一绝缘层，第一下铜层，包括第一下焊盘的第二电路层和第一通孔的第一双面基板; 制备包括第二绝缘层，第三下铜层，包括第二下焊盘的第四电路层和第二通孔的第二双面基板; 在所述第二电路层和所述第四电路层之间设置第三绝缘层，使得所述第一下焊盘和所述第二下焊盘通过导电凸块彼此电连接; 以及形成第一电路层，所述第一电路层包括在所述第一下铜层上连接到所述第一通孔的第一电路图案，并形成第三电路层，所述第三电路层包括在所述第三下铜层上连接到所述第二通孔的第三电路图案。

公开(公告)号：US08085546B2

公开(公告)日：2011-12-27

申请号：US12901104

申请日：2010-10-08

Applicant: Ayao Niki

Inventor： Ayao Niki

IPC: H05K7/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A coreless multilayer printed wiring board including a coreless layer having an opening, a conductive film formed on an upper surface of the coreless layer and closing one end of the opening of the coreless layer, a via-hole formed in the opening of the coreless layer, a first resin layer formed on the coreless layer and the conductive film and having an opening reaching to the conductive film, a via-hole formed in the opening of the first resin layer, a second resin layer formed on the upper surface of the first resin layer and having an opening, a via-hole formed in the opening of the second resin layer. The via-holes formed in the first and second resin layers are open in the direction opposite to the direction in which the via-hole formed in the coreless layer is open.

Abstract translation: 一种无芯多层印刷线路板，包括具有开口的无芯层，形成在无芯层的上表面上并封闭无芯层的开口的一端的导电膜，形成在无芯层的开口中的通孔 形成在无芯层和导电膜上并具有到达导电膜的开口的第一树脂层，形成在第一树脂层的开口中的通孔，形成在第一树脂层的上表面上的第二树脂层 树脂层并具有开口，形成在第二树脂层的开口中的通孔。 形成在第一和第二树脂层中的通孔在与形成在无芯层中的通孔开放的方向相反的方向上是开放的。

公开(公告)号：US08027169B2

公开(公告)日：2011-09-27

申请号：US11555881

申请日：2006-11-02

Applicant: Ayao Niki

Inventor： Ayao Niki

IPC: H05K7/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract translation: 多层印刷线路板包括一个或多个具有通孔的树脂层和具有通孔的芯层。 在一个或多个树脂层中形成的通孔在与芯层中形成的通路孔打开的方向相反的方向上开口。 一种制造多层印刷线路板的方法包括制备单面或双面覆铜层压板的步骤; 通过加工覆铜层压板来形成焊盘的步骤; 在覆铜层压板的上表面上形成树脂层的步骤，在树脂层中形成通孔的开口，然后形成通孔; 以及在覆铜层压板的下表面中形成用于通孔的开口，然后形成通孔的步骤。

公开(公告)号：US20110155439A1

公开(公告)日：2011-06-30

申请号：US12969961

申请日：2010-12-16

Applicant: Tomoko Yamada

Inventor： Tomoko Yamada

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K3/4652 ,  H05K3/421 ,  H05K2201/09527 ,  H05K2201/096

Abstract: The multilayer wiring substrate includes: a first insulating layer comprising a first surface and a second surface opposite to the first surface; a second insulating layer on the first surface of the first insulating layer; a first wiring pattern on the second surface of the first insulating layer; a second wiring pattern on a surface of the second insulating layer; a first via formed through the first insulating layer; a second via formed through the second insulating layer; and a third wiring pattern formed on the first surface of the first insulating layer and embedded in the second insulating layer, the third wiring pattern having a hole therethrough. A diameter of the hole is smaller than each diameter of the first and second vias. The first via and the second via are connected to each other through a metal filled in the hole of the third wiring pattern.

Abstract translation: 多层布线基板包括：第一绝缘层，包括第一表面和与第一表面相对的第二表面; 在所述第一绝缘层的所述第一表面上的第二绝缘层; 在第一绝缘层的第二表面上的第一布线图案; 在所述第二绝缘层的表面上的第二布线图案; 通过所述第一绝缘层形成的第一通孔; 通过第二绝缘层形成的第二通孔; 以及形成在第一绝缘层的第一表面上并嵌入第二绝缘层中的第三布线图案，第三布线图案具有穿过其的孔。 孔的直径小于第一和第二通孔的每个直径。 第一通孔和第二通孔通过填充在第三布线图案的孔中的金属彼此连接。