公开(公告)号：US20160003446A1

公开(公告)日：2016-01-07

申请号：US14850876

申请日：2015-09-10

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Yei-How HO

IPC: F21V7/22 ,  F21V7/04 ,  F21V5/04

CPC classification number: F21V7/22 ,  F21V5/04 ,  F21V7/041 ,  F21V7/045 ,  F21Y2115/10 ,  H01L33/0095 ,  H01L33/58 ,  H01L33/60 ,  H05K1/0274 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: A light-emitting assembly and a method for manufacturing the same are provided. The light-emitting assembly includes a circuit board with a light-emitting element and a plurality of optical microstructures disposed thereon. The optical microstructures adjacent to the light-emitting element absorb or guide a portion of light emitted from the light-emitting element.

公开(公告)号：US20150155453A1

公开(公告)日：2015-06-04

申请号：US14617067

申请日：2015-02-09

Applicant: Heraeus Noblelight GmbH

Inventor： Michael PEIL ,  Florin OSWALD ,  Harald MAIWEG

IPC: H01L33/56 ,  H01L27/15 ,  H01L27/144 ,  H01L31/0203

CPC classification number: H01L33/54 ,  F21K9/90 ,  F21Y2115/10 ,  H01L21/56 ,  H01L23/24 ,  H01L23/3121 ,  H01L27/1446 ,  H01L27/15 ,  H01L31/0203 ,  H01L31/02325 ,  H01L33/56 ,  H01L2924/0002 ,  H01L2933/005 ,  H05K1/0274 ,  H05K3/284 ,  H05K2201/0108 ,  H05K2201/0162 ,  H05K2201/0175 ,  H05K2201/09909 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2203/0126 ,  H01L2924/00

Abstract: A method is provided for coating an optoelectronic chip-on-board module, including a flat substrate populated with one or more optoelectronic components, having a transparent, UV-resistant, and temperature-resistant coating made of one or more silicones. A corresponding optoelectronic chip-on-board module and a system having multiple optoelectronic chip-on-board modules are also provided. The method includes the following steps: a) preheating the substrate to be coated to a first temperature; b) applying on the preheated substrate a dam that encloses a surface area or partial area of the substrate to be coated, the dam being made of a first, heat-curable, highly reactive silicone that cures at the first temperature; c) filling the surface area or partial area of the substrate enclosed by the dam with a liquid second silicone; and d) curing the second silicone.

Abstract translation: 提供了一种用于涂覆光电芯片模块的方法，其包括具有一个或多个光电子部件的平坦基板，其具有由一个或多个硅氧烷构成的透明的耐紫外线和耐温涂层。 还提供了相应的光电芯片组模块和具有多个光电芯片模块的系统。 该方法包括以下步骤：a）将待涂覆的基材预热至第一温度; b）在预热的基底上施加包围待涂覆的基底的表面积或部分区域的坝，所述坝由在第一温度下固化的第一可热固化的高反应性硅树脂制成; c）用液体第二硅胶填充由大坝封闭的基板的表面积或部分区域; 和d）固化第二硅氧烷。

公开(公告)号：US20150011128A1

公开(公告)日：2015-01-08

申请号：US13933288

申请日：2013-07-02

Applicant: Germane Systems, LC

Inventor： MICHAEL STOCK ,  SCOTT SEMMLER

IPC: H01R13/533 ,  H05K3/00 ,  H05K7/14

CPC classification number: H01R13/533 ,  H01R12/7029 ,  H05K1/141 ,  H05K3/00 ,  H05K3/366 ,  H05K7/1405 ,  H05K2201/09045 ,  H05K2201/09909 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2201/10606 ,  Y10T29/49117 ,  Y10T156/1089

Abstract: A circuit board that is to be mounted in a connector socket includes a plurality of electrical connectors located along a side edge of the circuit board. Retention bosses are formed on first and second opposite sides of the circuit board, each of the retention bosses protruding from a surface of the circuit board and extending parallel to and adjacent to the first edge of the circuit board. When the first edge of the circuit board is inserted into a slot of a connector socket, contact surfaces of the first and second retention bosses contact top surfaces of the connector socket to help immobilize the circuit board with respect to the connector socket. Adhesive layers on the contact surfaces of the first and second retention bosses may adhere to the top surfaces of the connector socket to help hold the circuit board immobile with respect to the connector socket.

公开(公告)号：US20140307359A1

公开(公告)日：2014-10-16

申请号：US14316012

申请日：2014-06-26

Applicant: DENSO CORPORATION ,  Murata Manufacturing Co., Ltd.

Inventor： Yuuki MIKAMI ,  Toru ITABASHI ,  Takahiko FURUTA ,  Ryoichi SHIRAISHI ,  Hiroaki NAKAMURA ,  Shigeki NISHIYAMA

IPC: H02H5/04

CPC classification number: H02H5/047 ,  H01H85/046 ,  H01H85/08 ,  H01H85/10 ,  H05K1/0265 ,  H05K1/0293 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10181

Abstract: An electronic control device includes a substrate, a plurality of component-mounted wires, a plurality of electronic components, a common wire, an interrupt wire and a protective layer. The component-mounted wires and the common wire are disposed on the substrate. The electronic components are mounted on the respective component-mounted wires and are coupled with the common wire. The interrupt wire is coupled between one component-mounted wire and the common wire, and is configured to melt in accordance with heat generated by an overcurrent to interrupt a coupling between the component-mounted wire and the common wire. The protective layer covers a surface of the substrate including the interrupt wire and defines an opening portion so that at least a portion of the interrupt wire is exposed.

Abstract translation: 电子控制装置包括基板，多个部件安装导线，多个电子部件，公共线，中断线和保护层。 组件安装线和公共线设置在基板上。 电子部件安装在相应的部件安装的导线上并与公共线耦合。 中断线耦合在一个部件安装的线和公共线之间，并且被配置为根据由过电流产生的热量熔化，以中断部件安装的线和公共线之间的耦合。 保护层覆盖包括中断线的基板的表面，并且限定开口部分，使得中断线的至少一部分被暴露。

公开(公告)号：US20140225257A1

公开(公告)日：2014-08-14

申请号：US14258300

申请日：2014-04-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/488

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。

公开(公告)号：US20140126166A1

公开(公告)日：2014-05-08

申请号：US13730408

申请日：2012-12-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Su Il Kim ,  Soon Jin Cho

IPC: H05K13/00 ,  H05K1/18

CPC classification number: H05K1/18 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H05K3/303 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/2036 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein is a method of forming a solder resist (SR) post, including: (A) forming an SR layer on a printed circuit board; (B) disposing a patterning film on an upper surface on the SR layer; (C) forming a plurality of openings in the patterning film or the SR layer; (D) filling SR ink in the openings and performing an exposure process to form a plurality of SR posts; (E) delaminating the patterning film; (F) removing an uncured portion of the SR ink on which the exposure process is performed; and (G) drying the plurality of SR posts.

Abstract translation: 本文公开了一种形成阻焊剂（SR）柱的方法，包括：（A）在印刷电路板上形成SR层; （B）在SR层的上表面上配置图案化膜; （C）在图案化膜或SR层中形成多个开口; （D）在开口中填充SR墨水并执行曝光处理以形成多个SR柱; （E）分层图形膜; （F）去除进行曝光处理的SR墨水的未固化部分; 和（G）干燥多个SR柱。

公开(公告)号：US20140008780A1

公开(公告)日：2014-01-09

申请号：US14006527

申请日：2012-07-20

Applicant: Mahiro Tsujino ,  Manabu Miyahara

Inventor： Mahiro Tsujino ,  Manabu Miyahara

IPC: H01L23/00

CPC classification number: H01L24/42 ,  H01L23/057 ,  H01L23/10 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/171 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/09909 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.

Abstract translation: 半导体器件壳体封装包括：基体，其上表面具有半导体器件的安装区域; 框架体，其具有设置在基体的上表面上的框状部分，围绕安装区域，以及从框状部分的内侧穿过其外侧的开口; 设置在所述开口中的平板状绝缘构件，从所述框体的内部延伸到其外部; 布线导体设置在绝缘构件的上表面上，从框体的内部延伸到其外部; 以及设置在所述绝缘构件的上表面的一部分上的金属膜，所述金属膜位于围绕所述布线导体的框架体的外侧。

公开(公告)号：US20130322913A1

公开(公告)日：2013-12-05

申请号：US13895277

申请日：2013-05-15

Applicant: CANON KABUSHIKI KAISHA

Inventor： Norikazu Sugiyama ,  Takahiro Yoneyama ,  Fumiyuki Yamatsuka ,  Osamu Mukataka ,  Kumiko Omori

IPC: G03G15/00 ,  H05K1/02

CPC classification number: H05K1/0296 ,  G03G15/80 ,  H05K1/0254 ,  H05K3/4007 ,  H05K2201/09909 ,  H05K2203/043

Abstract: The circuit board includes a contact for supplying power, in which the contact includes plural copper foil patterns each having a predetermined width, the plural copper foil patterns being formed radially from a center of the contact and connected to each other at the center of the contact. Accordingly, it is possible to enhance contact reliability of the contact while suppressing cost for connecting a high-voltage board to an image forming unit.

Abstract translation: 电路板包括用于供电的触点，其中触点包括多个具有预定宽度的铜箔图案，多个铜箔图形从触点的中心径向形成，并在触点的中心彼此连接 。 因此，可以在抑制高压基板与图像形成单元的连接成本的同时提高接触的接触可靠性。

公开(公告)号：US08599328B2

公开(公告)日：2013-12-03

申请号：US13192021

申请日：2011-07-27

Applicant: Sae Sam Jang ,  Sung Won Chung ,  Jae Hwan Chun ,  Jin Min Chung ,  Kyung Rok Ko

Inventor： Sae Sam Jang ,  Sung Won Chung ,  Jae Hwan Chun ,  Jin Min Chung ,  Kyung Rok Ko

IPC: G02F1/1333

CPC classification number: G02F1/133308 ,  G02F1/1339 ,  G02F2001/133311 ,  G02F2001/13332 ,  G02F2202/22 ,  H05K5/0213 ,  H05K2201/09909

Abstract: A liquid crystal display includes a liquid crystal panel displaying images, a plurality of gate circuit chips-on-film connected to the liquid crystal panel and supplying gate driving signals to the liquid crystal panel, a plurality of data circuit chips-on-film connected to the liquid crystal panel and supplying data driving signals to the liquid crystal panel, a gate printed circuit board (PCB) connected to the gate circuit chips-on-film, a data printed circuit board (PCB) connected to the data circuit chips-on-film, a backlight assembly supplying light to the liquid crystal panel, and a top chassis fixing the liquid crystal panel and the backlight assembly, and including an upper surface and a lower surface, wherein the data printed circuit board (PCB) is disposed corresponding to the lower surface of the top chassis, and a plurality of drain holes are disposed in the lower surface of the top chassis.

Abstract translation: 液晶显示器包括显示图像的液晶面板，与液晶面板连接的多个栅极电路芯片，并将栅极驱动信号提供给液晶面板，多个数据电路芯片在膜上连接 向液晶面板提供数据驱动信号，向薄膜上的栅极电路连接的栅极印刷电路板（PCB），与数据电路芯片连接的数据印刷电路板（PCB） 在液晶面板上提供光的背光组件和固定液晶面板和背光组件的顶板，并且包括上表面和下表面，其中数据印刷电路板（PCB）被布置 对应于顶部底盘的下表面，并且多个排水孔设置在顶部底盘的下表面中。

公开(公告)号：US08584924B2

公开(公告)日：2013-11-19

申请号：US10506611

申请日：2003-03-06

Applicant: Jürgen Schulz-Harder

Inventor： Jürgen Schulz-Harder

IPC: B23K20/24

CPC classification number: C04B37/021 ,  B32B2311/12 ,  C04B2237/407 ,  H05K1/0266 ,  H05K1/0306 ,  H05K3/061 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/38 ,  H05K3/383 ,  H05K2201/0355 ,  H05K2201/09909 ,  H05K2201/09936 ,  H05K2203/0369 ,  H05K2203/0571 ,  H05K2203/0588

Abstract: The invention relates to a novel process for producing a metal ceramic substrate, especially a copper-ceramic substrate, in which at least one metal foil at a time is applied to the surface sides of a ceramic layer or a ceramic substrate using a high temperature bonding process and the metal foil is structured on at least one surface side for forming conductive tracks, contact surfaces, and the like.

Abstract translation: 本发明涉及一种用于制造金属陶瓷基板，特别是铜陶瓷基板的新方法，其中使用高温接合将至少一个金属箔一次施加到陶瓷层或陶瓷基板的表面侧 工艺，并且金属箔被构造在用于形成导电轨道，接触表面等的至少一个表面侧上。