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公开(公告)号：US20170329377A1
公开(公告)日：2017-11-16
申请号：US15668771
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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公开(公告)号：US09760409B2
公开(公告)日：2017-09-12
申请号：US15162709
申请日：2016-05-24
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Mark Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Daniel Borkowski , Vivek Garg , Chelsea Akturan , Avinash N. Ananthakrishnan
CPC classification number: G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.
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公开(公告)号：US20170083076A1
公开(公告)日：2017-03-23
申请号：US15367330
申请日：2016-12-02
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
CPC classification number: G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
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公开(公告)号：US09535487B2
公开(公告)日：2017-01-03
申请号：US14855553
申请日：2015-09-16
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
CPC classification number: G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。 功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。 使用表中的信息，可以更新电源管理功能的至少一个设置。 描述和要求保护其他实施例。
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公开(公告)号：US09405351B2
公开(公告)日：2016-08-02
申请号：US13716712
申请日：2012-12-17
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner , Vivek Garg , Chris Poirier , Martin T. Rowland
CPC classification number: G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F9/5044 , G06F9/505 , G06F13/00 , G06F15/17325 , G06T1/20 , Y02D10/126
Abstract: In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。 功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US12282377B2
公开(公告)日：2025-04-22
申请号：US17358224
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Pritesh P. Shah , Suresh Chemudupati , Alexander Gendler , David Hunt , Christopher M. Macnamara , Ofer Nathan , Adwait Purandare , Ankush Varma
IPC: G06F1/3287 , G06F1/3228 , G06F1/3296 , G06F9/50
Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.
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公开(公告)号：US11886918B2
公开(公告)日：2024-01-30
申请号：US17717859
申请日：2022-04-11
Applicant: INTEL CORPORATION
Inventor： Ankush Varma , Nikhil Gupta , Vasudevan Srinivasan , Krishnakanth Sistla , Nilanjan Palit , Abhinav Karhu , Eugene Gorbatov , Eliezer Weissmann
CPC classification number: G06F9/5027 , G06F9/4812 , G06F9/4881 , G06F9/542 , G06F15/8038
Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.
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公开(公告)号：US11579944B2
公开(公告)日：2023-02-14
申请号：US16190806
申请日：2018-11-14
Applicant: Intel Corporation
Inventor： Daniel J. Ragland , Guy M. Therien , Ankush Varma , Eric J. DeHaemer , David T. Mayo , Ariel Gur , Yoav Ben-Raphael , Mark P. Seconi
IPC: G06F9/50 , G06F9/52 , G06F13/20 , G06F1/28 , G06F1/324 , G06F1/3203 , G06F1/3296 , G06F1/3287
Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
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公开(公告)号：US11543878B2
公开(公告)日：2023-01-03
申请号：US17042804
申请日：2018-05-01
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Eric Dehaemer , Alexander Gendler , Nadav Shulman , Krishnakanth Sistla , Nir Rosenzweig , Ankush Varma , Ariel Szapiro , Arye Albahari , Ido Melamed , Nir Misgav , Vivek Garg , Nimrod Angel , Adwait Purandare , Elkana Korem
IPC: G06F1/32 , G06F9/4401 , G06F1/329 , G06F1/3206 , G06F9/30 , G06F9/48
Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.
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公开(公告)号：US20220413720A1
公开(公告)日：2022-12-29
申请号：US17359334
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Adwait Purandare , Ian Steiner , Vasudevan Srinivasan , Ankush Varma , Nikhil Gupta , Stanley Chen
IPC: G06F3/06
Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.
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