公开(公告)号：US09781830B2

公开(公告)日：2017-10-03

申请号：US14205337

申请日：2014-03-11

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, Jr.

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K1/036 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/0713 ,  H05K2203/0723

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20170265298A1

公开(公告)日：2017-09-14

申请号：US15081623

申请日：2016-03-25

Applicant: Multek Technologies Limited

Inventor： Mark Zhang ,  Kwan Pen ,  Pui Yin Yu

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/06 ,  H05K3/42 ,  H05K1/03 ,  H05K3/46

CPC classification number: H05K3/048 ,  H05K1/036 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09109 ,  H05K2201/0989 ,  H05K2203/0228 ,  H05K2203/1383

Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.

公开(公告)号：US20170263546A1

公开(公告)日：2017-09-14

申请号：US15605920

申请日：2017-05-25

Applicant: BRIDGE SEMICONDUCTOR CORPORATION

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K3/4647 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/13099

Abstract: A wiring board includes an electrical isolator laterally surrounded by a base board and a molding compound. The electrical isolator is inserted into a through opening of the base board and has a thickness greater than that of the base board. The molding compound covers the top side of the base board and sidewalls of the electrical isolator, and provides a reliable interface for deposition of a routing circuitry thereon. The base board can serve as an alignment guide for isolator placement or/and provide another routing to enhance electrical routing flexibility for the wiring board.

公开(公告)号：US20170247524A1

公开(公告)日：2017-08-31

申请号：US15129633

申请日：2015-03-26

Applicant: SAINT-GOBAIN CENTRE DE RECHERCHES ET D'ETUDES EUROPEEN

Inventor： Stéphane RAFFY

IPC: C08K3/22 ,  H05K1/16 ,  H05K9/00

CPC classification number: C08K3/22 ,  C08K2003/2237 ,  C08K2201/001 ,  H05K1/162 ,  H05K9/0083 ,  H05K2201/0187 ,  H05K2201/0209

Abstract: Polymer-ceramic composites, in particular for the field of electronics, include grains of titanium suboxides of general formulation TiOx in which x is between 1.00 and 1.99, limits included, and/or of barium and/or strontium titanate suboxides of general formulation Ba(1-m)SrmTiOy in which y is between 1.50 and 2.99, limits included, and m is between 0 and 1, limits included.

公开(公告)号：US09743526B1

公开(公告)日：2017-08-22

申请号：US15040564

申请日：2016-02-10

Applicant: International Business Machines Corporation ,  SHINKO ELECTRIC INDUSTRIES CO., LTD

Inventor： Edmund Blackshear ,  Keiichi Hirabayashi ,  Yoichi Miyazawa ,  Brian W. Quinlan ,  Junji Sato

IPC: H05K1/18 ,  H05K3/32 ,  H05K3/40 ,  H05K1/11 ,  H05K3/46 ,  H05K3/00 ,  H05K1/02

CPC classification number: H05K1/185 ,  H05K1/0269 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/0055 ,  H05K3/32 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2203/1572 ,  H05K2203/16 ,  H05K2203/166

Abstract: A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.

公开(公告)号：US09736927B2

公开(公告)日：2017-08-15

申请号：US14875241

申请日：2015-10-05

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Suk Hyeon Cho ,  Yoong Oh ,  Young Gwan Ko ,  Yong Ho Baek ,  Young Kuk Ko

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46 ,  H05K1/18 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/0271 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/15788 ,  H05K1/038 ,  H05K1/115 ,  H05K1/181 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0909 ,  H05K2201/09536 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/10674

Abstract: There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board include a glass plate, an insulating member penetrating through the glass plate, insulating layers disposed on a first surface and a second surface of the glass plate, and a via through the insulating member.

公开(公告)号：US20170231094A1

公开(公告)日：2017-08-10

申请号：US15040564

申请日：2016-02-10

Applicant: International Business Machines Corporation ,  SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Edmund Blackshear ,  Keiichi Hirabayashi ,  Yoichi Miyazawa ,  Brian W. Quinlan ,  Junji Sato

IPC: H05K1/18 ,  H05K3/40 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K3/32 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K1/0269 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/0055 ,  H05K3/32 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2203/1572 ,  H05K2203/16 ,  H05K2203/166

Abstract: A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.

公开(公告)号：US09683132B2

公开(公告)日：2017-06-20

申请号：US15261624

申请日：2016-09-09

Applicant: Syed Taymur Ahmad ,  Bruce Acton

Inventor： Syed Taymur Ahmad ,  Bruce Acton

IPC: H05K1/00 ,  C09D183/04 ,  H05K3/28 ,  H05K7/14 ,  H05K1/03 ,  C09D133/16 ,  H01R12/71 ,  H05K3/40

CPC classification number: C09D183/04 ,  C09D133/16 ,  H01R12/716 ,  H05K1/0353 ,  H05K3/282 ,  H05K3/284 ,  H05K3/285 ,  H05K3/40 ,  H05K7/1427 ,  H05K2201/0162 ,  H05K2201/0187 ,  H05K2203/1173 ,  H05K2203/121 ,  H05K2203/1322 ,  H05K2203/1338 ,  H05K2203/1361 ,  H05K2203/1366 ,  H05K2203/1572

Abstract: Methods for protecting an electronic device from contaminants by applying different polymeric materials to different vital components of a device are disclosed. In one embodiment, the method comprises applying a first polymer, such as an acrylic-based polymer, to one or more connectors and components located on the printed circuit board of the device. The method further comprises applying a second polymer, such as a silicone-based polymer, to different connectors and components on the printed circuit board. The method leads to different components being coated with a different polymers, without the need for multilayer coatings on any component. Electronic devices that are protected by such polymeric, hydrophobic coatings are also disclosed. Non-limiting examples of such devices include smart phones, computers, and gaming devices.

公开(公告)号：US20170105289A1

公开(公告)日：2017-04-13

申请号：US15299996

申请日：2016-10-21

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroyuki OSUGA ,  Sohei SAMEJIMA ,  Kazuhito SAKURADA ,  Akira YAGASAKI ,  Tatsuya HINATA

IPC: H05K3/42 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K3/42 ,  H05K1/0243 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/115 ,  H05K1/181 ,  H05K3/303 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0323 ,  H05K2203/0228

Abstract: On a printed wiring board obtained by a method of manufacturing a printed board, a predetermined component is to be mounted on at least one of a front surface side and a back surface side. The manufacturing method includes preparing a CFRP core, forming a through hole so as to penetrate the CFRP core from the front surface side to the back surface side and include a region in which the component is to be mounted when viewed in a plan view, and embedding a GFRP core having insulating properties within the through hole by filling the through hole with a resin having insulating properties and curing the resin. According to the manufacturing method, the component mounted on the printed board is not affected by a stray capacitance due to a CFRP, and it is not difficult to form a circuit.

公开(公告)号：US09596766B2

公开(公告)日：2017-03-14

申请号：US14173554

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： David N. Shykind ,  James A. McCall

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/03 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/10 ,  H05K1/0216 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0366 ,  H05K3/0052 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09972 ,  H05K2203/1554 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49798 ,  Y10T428/24058 ,  Y10T428/24917 ,  Y10T428/249935 ,  Y10T428/24994 ,  Y10T428/249943 ,  Y10T428/249946 ,  Y10T442/2926 ,  Y10T442/2992 ,  Y10T442/3065

Abstract: A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.

Abstract translation: 这里描述了制造电路板的方法。 该方法可以包括添加树脂，形成第一和第二玻璃纤维纤维，以及形成能够传输电信号的第一和第二信号线迹线。 在一些实例中，第一信号线迹线附近的玻璃纤维和树脂材料之间的比率类似于第二信号线迹线附近的玻璃纤维和树脂材料之间的比率。 在一些示例中，第一和第二玻璃纤维光纤在第一和第二信号线迹线附近对角地交叉。 在一些示例中，第一和第二玻璃纤维纤维以锯齿形图案在第一和第二信号线迹线附近交叉。