公开(公告)号：US20130175076A1

公开(公告)日：2013-07-11

申请号：US13739454

申请日：2013-01-11

Applicant: E.G.O. Elektro-Geratebau GmbH

Inventor： Axel Hiller

IPC: H05K1/11 ,  H05K3/34

CPC classification number: H05K1/11 ,  H05K1/0265 ,  H05K3/34 ,  H05K2201/0305 ,  H05K2201/09572 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: The disclosure relates to a component carrier or printed circuit board for electronic components. According to embodiments, a component carrier may include a first contact face for a contact to a first component, a second contact face for a contact to a second component as well as a conductor track that electrically couples the first and the second contact face. The conductor track may include a conductor recess along the conductor track extending through the printed circuit board. An electric conductor may be arranged in the conductor recess extending over the entire course thereof and electrically coupled to the conductor track.

Abstract translation: 本公开涉及用于电子部件的部件载体或印刷电路板。 根据实施例，部件载体可以包括用于与第一部件的接触的第一接触面，用于与第二部件的接触的第二接触面以及电耦合第一和第二接触面的导体轨道。 导体轨道可以包括沿着延伸穿过印刷电路板的导体轨迹的导体凹部。 电导体可以布置在导体凹部中，在其整个过程上延伸并且电耦合到导体轨道。

公开(公告)号：US20130130418A1

公开(公告)日：2013-05-23

申请号：US13512328

申请日：2010-11-04

Applicant: Young Seob Lee

Inventor： Young Seob Lee

IPC: H01L33/64

CPC classification number: H01L33/647 ,  F21K9/00 ,  F21V29/20 ,  F21V29/70 ,  F21V29/89 ,  F21W2131/103 ,  F21Y2115/10 ,  H01L33/642 ,  H01L2224/48091 ,  H05K1/0206 ,  H05K3/0047 ,  H05K3/0061 ,  H05K2201/0305 ,  H05K2201/09854 ,  H05K2201/10106 ,  H05K2203/1572 ,  H01L2924/00014

Abstract: The present invention relates to a method for manufacturing large lighting which uses a power LED, such as for large LED lighting for street lamps, which incorporates a heat dissipation device that has the ability to dissipate heat with natural convection to maintain ambient temperature. The disclosed method is novel applied technology for producing a large LED lighting, such as for street lamps, which has a power LED device with a unique, rear heat dissipation capability. In addition to maximum thermal efficiency by heat dissipation, the present LED lighting system also increases luminous efficiency by providing high light emission with only a small quantity of LED power.

Abstract translation: 本发明涉及一种制造大型照明的方法，其使用功率LED，例如用于路灯的大型LED照明，其包括具有通过自然对流散热以维持环境温度的能力的散热装置。 所公开的方法是用于生产诸如路灯的大型LED照明的新颖应用技术，其具有具有独特的后部散热能力的功率LED装置。 除了通过散热的最大热效率之外，目前的LED照明系统还通过仅提供少量LED功率的高发光量来提高发光效率。

公开(公告)号：US20120325533A1

公开(公告)日：2012-12-27

申请号：US13453211

申请日：2012-04-23

Applicant: Hideaki YOSHIMURA

Inventor： Hideaki YOSHIMURA

IPC: H05K1/11 ,  B23K31/02

CPC classification number: H05K3/4623 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0305 ,  H05K2203/061

Abstract: A method of manufacturing a multilayer circuit board includes forming a prepreg on a surface of a first circuit board including a first region in which a plated-through hole is formed and a second region in which a solid pattern is formed, the prepreg having a first hole reaching the plated-through hole and a second hole reaching the solid pattern, filling the first hole with a conductive paste, and pressing a second circuit board on the prepreg to laminate the first circuit board and the second circuit board to each other after filling the first hole with the conductive paste.

Abstract translation: 一种制造多层电路板的方法包括在包括形成有电镀通孔的第一区域和形成固体图形的第二区域的第一电路板的表面上形成预浸料坯，所述预浸料坯具有第一 到达电镀通孔的孔和到达固体图案的第二孔，用导电膏填充第一孔，并且在预浸料上挤压第二电路板，以在填充之后将第一电路板和第二电路板彼此层压 第一个孔与导电膏。

公开(公告)号：US08310057B2

公开(公告)日：2012-11-13

申请号：US12963887

申请日：2010-12-09

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/48

CPC classification number: H01L24/10 ,  H01L21/486 ,  H01L21/563 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05647 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A substrate includes an insulating film in which a penetrating hole is formed, the penetrating hole extending between a first surface of the insulating film and a second surface of the insulating film opposite to the first surface of the insulating film. A wiring pattern is adhered to the first surface of the insulating film by an adhesive material. A first portion of the wiring pattern is formed over the penetrating hole, and a part of the adhesive material is formed on an internal wall surface forming the penetrating hole so as not to stop up the penetrating hole. An external electrode contacts the first portion of the wiring pattern and projects through the penetrating hole and extends beyond the second surface of the insulating film.

Abstract translation: 基板包括绝缘膜，其中形成有穿透孔，所述穿透孔在绝缘膜的第一表面和绝缘膜的与绝缘膜的第一表面相对的第二表面之间延伸。 通过粘合剂材料将布线图案粘附到绝缘膜的第一表面。 布线图案的第一部分形成在穿透孔的上方，并且粘合材料的一部分形成在形成穿透孔的内壁表面上，以便不停止穿透孔。 外部电极与布线图案的第一部分接触并且穿过该穿孔延伸出绝缘膜的第二表面。

公开(公告)号：US08115110B2

公开(公告)日：2012-02-14

申请号：US11822137

申请日：2007-07-02

Applicant: Leon M. Khilchenko ,  Mark W. Gailus

Inventor： Leon M. Khilchenko ,  Mark W. Gailus

IPC: H05K1/11

CPC classification number: H05K3/4038 ,  H05K1/0298 ,  H05K3/321 ,  H05K3/3447 ,  H05K3/4046 ,  H05K3/4069 ,  H05K2201/0305 ,  H05K2201/0919 ,  H05K2201/10234 ,  H05K2201/1059 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/1446 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: What is provided is a multi-layer PCB having a plurality of stacked dielectric layers, a conductor disposed on at least one of the plurality of dielectric layers, and a non-conductive via extending through at least a portion of the plurality of dielectric layers to intersect the conductor. A conductive body in an activated state is introduced into the non-conductive via, and upon contacting the conductor, the activated state conductive body adheres to the conductor. The activated state conductive body is then effected to a deactivated state, wherein the conductive body is affixed to the conductor to provide an electrical connection thereto.

Abstract translation: 提供的是具有多个堆叠的电介质层的多层PCB，设置在多个电介质层中的至少一个介质层上的导体，以及延伸穿过多个电介质层的至少一部分的非导电通孔， 与导体相交。 处于激活状态的导电体被引入到非导电通孔中，并且在与导体接触时，活化状态导电体粘附到导体。 然后使激活状态的导电体进入去激活状态，其中导电体固​​定到导体以提供与其的电连接。

公开(公告)号：US08106408B2

公开(公告)日：2012-01-31

申请号：US12484196

申请日：2009-06-13

Applicant: Takuma Ban ,  Michihide Sasada ,  Masanobu Okayasu

Inventor： Takuma Ban ,  Michihide Sasada ,  Masanobu Okayasu

IPC: H01L31/12

CPC classification number: H01L31/0203 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01S5/02212 ,  H01S5/06226 ,  H05K1/0219 ,  H05K1/028 ,  H05K1/147 ,  H05K1/189 ,  H05K3/28 ,  H05K3/3421 ,  H05K3/3447 ,  H05K2201/0305 ,  H05K2201/09727 ,  H05K2201/10121 ,  H05K2201/10659 ,  H01L2924/00014

Abstract: A metal pattern for a high frequency signal is patterned on a flexile substrate, and the flexile substrate is bent in such a way as to form a substantially right angle at a spot corresponding to an end of the metal pattern for the signal. And an end of the metal pattern is fixedly attached to a lead pin for signaling, attached to a stem, for electrical continuity, so as to be in a posture horizontal with each other. Meanwhile, a part of the lead pins attached to the stem, being in such a state as penetrated through respective holes provided in the flexible substrate, is fixedly attached to a part of metal patterns provided on the flexible substrate so as to ensure electrical continuity therebetween.

Abstract translation: 用于高频信号的金属图案在柔性基板上被图案化，并且柔性基板被弯曲成在对应于该信号的金属图案的端部的点处形成基本上直角。 并且金属图案的端部固定地附接到引线销，用于发信号通知，连接到杆上以进行电连续性，以便处于相互水平的姿势。 同时，安装在杆上的引脚的一部分处于处于设置在柔性基板上的相应孔的穿透状态下，固定地附接到设置在柔性基板上的金属图案的一部分，以确保其间的电连续性 。

公开(公告)号：US20110138620A1

公开(公告)日：2011-06-16

申请号：US12999834

申请日：2009-05-25

Applicant: Ulrich Schaaf ,  Andreas Kugler

Inventor： Ulrich Schaaf ,  Andreas Kugler

IPC: H05K3/30

CPC classification number: H01L24/18 ,  H01L21/4825 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/18 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/10674 ,  H05K2203/302 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing an electronic assembly, including at least one electronic component and a circuit trace structure, by which the at least one electronic component is contacted. In the method, a conductive foil is patterned in a first step to form the circuit trace structure. In a second operation, the circuit trace structure is equipped with the at least one electronic component. In a final operation, another foil is laminated onto the conductive foil equipped with the at least one electronic component on the side on which the conductive foil is equipped with the at least one electronic component.

Abstract translation: 一种用于制造电子组件的方法，其包括至少一个电子部件和电路迹线结构，通过该电子部件和电路迹线结构与所述至少一个电子部件接触。 在该方法中，在第一步骤中对导电箔进行构图以形成电路迹线结构。 在第二操作中，电路迹线结构配备有至少一个电子部件。 在最后的操作中，将另一箔层压到配备有至少一个电子部件的导电箔上，导电箔配备有至少一个电子部件。

公开(公告)号：US07862153B2

公开(公告)日：2011-01-04

申请号：US11882058

申请日：2007-07-30

Applicant: Yasuhiko Maeda

Inventor： Yasuhiko Maeda

IPC: B41J2/14 ,  B41J2/16

CPC classification number: B41J2/14233 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/03 ,  H05K3/4038 ,  H05K3/4069 ,  H05K2201/0305 ,  H05K2203/0425

Abstract: The electrical wiring structure includes an electrical connection section where a first electrode and a second electrode are connected, wherein: the electrical connection section is formed by a first alloy containing at least gallium metal; and the first alloy has a melting point lower than 30° C.

Abstract translation: 电气配线结构包括连接第一电极和第二电极的电连接部，其中：电连接部由至少含有金属镓的第一合​​金形成; 第一合金的熔点低于30℃。

公开(公告)号：US20100117245A1

公开(公告)日：2010-05-13

申请号：US12691255

申请日：2010-01-21

Applicant: Chonghua Zhong

Inventor： Chonghua Zhong

IPC: H01L23/488 ,  H05K1/11

CPC classification number: H01L23/5382 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0293 ,  H05K3/321 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/09381 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/173 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.

Abstract translation: 提供了用于集成电路封装基板，集成电路封装以及用于组装其的工艺的方法，系统和装置。 用于倒装芯片集成电路封装的衬底包括具有相对的第一和第二表面的衬底本体。 焊接掩模层覆盖基板主体的第一表面的至少一部分。 第一和第二导电特征形成在衬底主体上。 第一导电特征是第一电信号网的一部分，第二导电特征是第二电信号网的一部分。 第一和第二导电特征被配置为通过施加导电材料选择性地电耦合在一起。 导电材料可以是导电环氧树脂，跳线，焊膏，焊球或将倒装芯片裸片耦合到衬底的焊料凸块。

公开(公告)号：US20100105201A1

公开(公告)日：2010-04-29

申请号：US12650093

申请日：2009-12-30

Applicant: Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

Inventor： Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

IPC: H01L21/60

CPC classification number: H05K3/303 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2201/2036 ,  Y02P70/613

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract translation: 半导体器件包括半导体封装，电路板和间隔保持元件。 半导体封装具有从主体突出的主体和引线。 电路板具有与引线电连接的第一焊盘。 间隔保持构件插入在电路板和主体之间。 间隔保持构件保持引线与第一焊盘之间的间隔。 因此，均匀地保持引线和焊盘之间的间隔，从而提高了半导体器件的热和/或机械可靠性。