公开(公告)号：US20230380068A1

公开(公告)日：2023-11-23

申请号：US18029945

申请日：2021-09-24

Applicant: Hitachi Astemo, Ltd.

Inventor： Takeshi IGARASHI ,  Katsuya OYAMA

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/31 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L23/12 ,  H01L23/3107 ,  H05K3/3431 ,  H05K2201/09372

Abstract: An object of the present invention is to provide an electronic control device capable of improving the connection life and reliability of solder connecting a printed circuit board and a QFN type semiconductor package. For this purpose, a printed circuit board 106 includes a first land 109 connected to a first metal terminal 104 via a solder 107, a second land 110 connected to a second metal terminal 105 via a solder 108, a third land 112 disposed on the outer peripheral side of a semiconductor package 101 with respect to the first land 109, and a resist 113 formed on the third land 112 so as to be in contact with the lower surface of a molding resin 103.

公开(公告)号：US20170165474A1

公开(公告)日：2017-06-15

申请号：US15357500

申请日：2016-11-21

Applicant: The Charles Stark Draper Laboratory, Inc.

Inventor： Maurice S. Karpman ,  Andrew Meuller

IPC: A61N1/05 ,  H05K1/09 ,  A61N1/36 ,  H05K3/40 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11 ,  H05K1/02

CPC classification number: A61N1/0502 ,  A61B5/04001 ,  A61B5/685 ,  A61B2562/043 ,  A61B2562/125 ,  A61N1/0551 ,  A61N1/36139 ,  H05K1/028 ,  H05K1/09 ,  H05K1/111 ,  H05K3/0026 ,  H05K3/40 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/05 ,  H05K2201/09372 ,  H05K2203/107

Abstract: The present disclosure describes a closely spaced array of penetrating electrodes. In some implementations, the electrodes of the array are spaced less than 50 μm apart. The present disclosure also describes methods for manufacturing the closely spaced array of penetrating electrodes. In some implementations, each row of electrode of the array is manufactured in-plane and then coupled to other rows of electrodes to form an array.

公开(公告)号：US09609741B1

公开(公告)日：2017-03-28

申请号：US15272201

申请日：2016-09-21

Applicant: CANON KABUSHIKI KAISHA

Inventor： Koji Noguchi

IPC: H05K7/00 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0203 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/06 ,  H05K2201/09227 ,  H05K2201/09372 ,  H05K2201/10015 ,  H05K2201/10545

Abstract: A printed wiring board has thereon an electronic component having a heat radiation pad, and an electrolytic capacitor provided for the electronic component. The printed wiring board further has thereon another electronic component having another heat radiation pad and exhibiting a higher heat value than that of the electronic component, and another electrolytic capacitor provided for the other electronic component. The heat radiation pad of the electronic component, a ground terminal of the electrolytic capacitor, the other heat radiation pad for the other electronic component, and another ground terminal of the other electrolytic capacitor are connected by using a ground conductor. In the ground conductor, a thermal resistance between the other heat radiation pad and other ground terminal is lower than the thermal resistance between the heat radiation pad and the ground terminal.

公开(公告)号：US20150313005A1

公开(公告)日：2015-10-29

申请号：US14406913

申请日：2012-06-15

Applicant: Masashi TAKABATAKE ,  Kenji KASHIWAGI

Inventor： Masashi TAKABATAKE ,  Kenji KASHIWAGI

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0213 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/111 ,  H05K3/3421 ,  H05K2201/0776 ,  H05K2201/09372 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y02P70/611

Abstract: [Object] There is suggested a printed circuit board capable of realizing impedance matching by securing joint reliability between signal pins of a surface mount connector and signal pin pads and preventing the reduction of impedance of signal pin pads while minimizing the reduction of a wirable area.[Solution] A printed circuit board equipped with a signal pin pad, which is soldered to a signal pin from a surface mount connector, and a ground layer located as a lower layer below the signal pin pad; wherein a fillet is formed around a joint area between the signal pin and the signal pin pad after soldering; wherein a cut-out portion is provided in the signal pin pad within a joint area with the signal pin; and wherein the size of the cut-out portion is set within the range of being completely covered within the joint area with the signal pin based on size tolerance of the signal pin, fabrication tolerance of the printed circuit board, and mount position tolerance of the surface mount connector.

Abstract translation: 提出了一种印刷电路板，其能够通过确保表面安装连接器的信号引脚和信号引脚焊盘之间的连接可靠性来实现阻抗匹配，并且防止信号引脚焊盘的阻抗减小，同时最小化可吸收区域的减少。 [解决方案]配备有从表面安装连接器焊接到信号引脚的信号引脚焊盘的印刷电路板和位于信号引脚焊盘下方的下层的接地层; 其中在焊接之后，在信号引脚和信号引脚焊盘之间的接合区域周围形成圆角; 其中在与所述信号引脚的接合区域内的所述信号引脚焊盘中设置切口部分; 并且其中，根据信号引脚的尺寸公差，印刷电路板的制造公差以及印刷电路板的安装位置公差，将切除部分的尺寸设定在与信号销的接合区域内完全覆盖的范围内 表面贴装连接器。

公开(公告)号：US20130269983A1

公开(公告)日：2013-10-17

申请号：US13534217

申请日：2012-06-27

Applicant: KAI-WEN WU

Inventor： KAI-WEN WU

IPC: H05K1/18 ,  G01R31/28 ,  H01R43/00

CPC classification number: H05K1/0253 ,  H01R12/53 ,  H01R13/6474 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/111 ,  H05K1/117 ,  H05K3/40 ,  H05K2201/09372 ,  H05K2201/10287 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A circuit board assembly includes a circuit board, at least one pad formed on the circuit board, and at least one connection line. Each of the at least one connection line includes a connection end connected to a respective one of the at least one pad and has the same resistance value as the respective pad.

公开(公告)号：US11991825B2

公开(公告)日：2024-05-21

申请号：US16392112

申请日：2019-04-23

Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yuanda Lu ,  Junjie Ma ,  Shipeng Wang ,  Ming Zhai ,  Jian Sang ,  Haiwei Sun ,  Dongjia Hao

IPC: F21V8/00 ,  H01R12/65 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/118 ,  H01R12/65 ,  H05K1/028 ,  H05K1/111 ,  H05K2201/09372 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/09781 ,  H05K2201/10378

Abstract: The present disclosure provides a flexible circuit board, a light bar, a light source and a display device. The light source includes a flexible circuit board having at least one effective welding portion and a light bar having at least one effective pad, the at least one effective welding portion being in one-to-one correspondence with the at least one effective pad, and the effective welding portion being fixed to a corresponding effective pad to transmit a signal loaded by itself to the corresponding effective pad. The flexible circuit board further includes at least one auxiliary welding portion, the light bar further includes at least one auxiliary pad that is in one-to-one correspondence with the at least one auxiliary welding portion, and the auxiliary welding portion is fixed to a corresponding auxiliary pad to enhance the firm fixing between the flexible circuit board and the light bar.

公开(公告)号：US20240006295A1

公开(公告)日：2024-01-04

申请号：US18466610

申请日：2023-09-13

Applicant: InnoLux Corporation

Inventor： Chung-Chun CHENG ,  Kuang-Ming FAN ,  Yao-Wen HSU

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/20 ,  H01L24/19 ,  H05K1/11 ,  H05K1/0268 ,  H01L2224/214 ,  H01L23/49822 ,  H01L2224/19 ,  H05K2201/09372 ,  H05K1/111

Abstract: A manufacturing method of electronic components includes the steps of: providing an insulating layer including a first region and a second region; providing a first metal layer disposed in the first region of the insulating layer; providing a second metal layer disposed on the first metal layer; providing a metal line in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer.

公开(公告)号：US11798875B2

公开(公告)日：2023-10-24

申请号：US17535167

申请日：2021-11-24

Applicant: InnoLux Corporation

Inventor： Chung-Chun Cheng ,  Kuang-Ming Fan ,  Yao-Wen Hsu

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/19 ,  H01L24/20 ,  H05K1/11 ,  H05K1/111 ,  H01L23/49822 ,  H01L2224/19 ,  H01L2224/214 ,  H05K1/0268 ,  H05K2201/0338 ,  H05K2201/0347 ,  H05K2201/09372

Abstract: An electronic component includes: an insulating layer; and a first metal bump disposed on the insulating layer and provided with: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

公开(公告)号：US09856140B2

公开(公告)日：2018-01-02

申请号：US14512105

申请日：2014-10-10

Applicant: OCE-TECHNOLOGIES B.V.

Inventor： Maikel A. J. Huygens ,  René J. Van Der Meer ,  Reinier Pannekoek ,  Alex N. Westland

IPC: G01R31/02 ,  B81C99/00 ,  B81B7/00 ,  B81C1/00 ,  G01R31/26 ,  H05K1/11 ,  B41J2/14 ,  B41J2/16 ,  H05K1/02

CPC classification number: B81C99/004 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1632 ,  B41J2/1635 ,  B41J2002/14241 ,  B41J2002/14459 ,  B41J2002/14491 ,  B81B7/007 ,  B81B2201/052 ,  B81B2207/03 ,  B81C1/00301 ,  G01R31/02 ,  G01R31/2601 ,  H05K1/0268 ,  H05K1/111 ,  H05K2201/09372

Abstract: A substrate plate is provided for at least one MEMS device to be mounted thereon. The MEMS device has a certain footprint on the substrate plate, and the substrate plate has a pattern of electrically conductive leads to be connected to electric components of the MEMS device. The pattern forms contact pads within the footprint of the MEMS device and includes at least one lead structure that extends on the substrate plate outside of the footprint of the MEMS device and connects a number of the contact pads to an extra contact pad. The lead structure is a shunt bar that interconnects a plurality of contact pads of the MEMS device and is arranged to be removed by means of a dicing cut separating the substrate plate into a plurality of chip-sized units. At least a major part of the extra contact pad is formed within the footprint of one of the MEMS devices.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.