公开(公告)号：US20230262906A1

公开(公告)日：2023-08-17

申请号：US17670394

申请日：2022-02-11

Applicant: Alibaba (China) Co., Ltd.

Inventor： Hui LIU

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/05

CPC classification number: H05K3/429 ,  H05K1/0298 ,  H05K1/05 ,  H05K2201/0959 ,  H05K2201/09981 ,  H05K2201/10007

Abstract: A substrate, a chip, a circuit package and a process of fabricating a substrate are presented. The substrate is provided between an integrated circuit and a printed circuit board, and comprises a core insulating and a buildup insulating layer. The first plated through hole is operable to provide ground through from the printed circuit board to the integrated circuit. The second plated through hole is operable to provide electrical communication carrying signals or power between the integrated circuit and the printed circuit board through the buildup insulating layers. The first plated through hole is formed in tubular shape defined an outer wall and an inner wall, and the second plated through hole is formed in the inner wall and is insulated with the first plated through hole.

公开(公告)号：US20230209729A1

公开(公告)日：2023-06-29

申请号：US18177461

申请日：2023-03-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Junichi NAKAMURA ,  Takeshi TAKAI ,  Yusuke KARASAWA ,  Yoshihisa KANBE ,  Shuhei MOMOSE ,  Toshiki SHIROTORI

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4661 ,  H05K1/115 ,  H05K2201/0212 ,  H05K2201/0959 ,  H05K2201/096

Abstract: A wiring board includes a core layer having a first through hole formed therein, a magnetic resin filled inside the first through hole, a second through hole formed in the magnetic resin, and a plating film covering an inner wall surface of the second through hole. The plating film includes an electroless plating film, and an electrolytic plating film. The electroless plating film makes direct contact with an inner wall surface of the second through hole.

公开(公告)号：US20230156908A1

公开(公告)日：2023-05-18

申请号：US17867624

申请日：2022-07-18

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/14

CPC classification number: H05K1/0222 ,  H01L23/49833 ,  H01L23/49822 ,  H05K1/144 ,  H05K1/024 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2201/0959

Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.

公开(公告)号：US20190172780A1

公开(公告)日：2019-06-06

申请号：US16266203

申请日：2019-02-04

Applicant: DAI NIPPON PRINTING CO., LTD.

Inventor： Satoru KURAMOCHI ,  Sumio KOIWA ,  Hidenori YOSHIOKA

IPC: H01L23/498 ,  H01L25/18 ,  H05K1/11 ,  H01L23/48 ,  H01L25/065 ,  H05K3/28 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/065 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81805 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H05K1/115 ,  H05K3/28 ,  H05K3/445 ,  H05K2201/09154 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2203/0594 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

公开(公告)号：US20180343748A1

公开(公告)日：2018-11-29

申请号：US15984458

申请日：2018-05-21

Applicant: FUJITSU LIMITED

Inventor： Yoshikazu Hirano ,  KINUKO MISHIRO ,  Toru Okada

IPC: H05K3/34 ,  H05K1/18 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K3/3447 ,  H05K1/116 ,  H05K1/184 ,  H05K3/3452 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2203/044 ,  H05K2203/045 ,  H05K2203/072 ,  H05K2203/0723

Abstract: A substrate on which an electronic component is soldered, includes an electronic component, a through hole positioned on the substrate and passing through the substrate, a solder that joins the through hole and a terminal of the electronic component inserted in the through hole, a pattern formed on a first surface of the substrate, the first surface facing a second surface on which the electronic component is placed, a first resist superimposed on the pattern, an exposed portion of which the pattern is exposed from the first resist around the through hole, and a second resist superimposed on the pattern and arranged between the through hole and the exposed portion.

公开(公告)号：US20180042123A1

公开(公告)日：2018-02-08

申请号：US15231515

申请日：2016-08-08

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K3/42 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09218 ,  H05K2201/09545 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.

公开(公告)号：US09870969B2

公开(公告)日：2018-01-16

申请号：US14193462

申请日：2014-02-28

Applicant: Advanced Micro Devices (Shanghai) Co., Ltd.

Inventor： I-Tseng Lee ,  Yu-Ling Hsieh

IPC: H05K1/02 ,  H01L23/13 ,  H05K3/00 ,  H05K1/03 ,  H05K3/34

CPC classification number: H01L23/13 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/01078 ,  H05K1/024 ,  H05K1/036 ,  H05K3/0052 ,  H05K3/0061 ,  H05K3/3452 ,  H05K2201/0209 ,  H05K2201/0959 ,  H05K2201/10674 ,  H01L2924/00

Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.

公开(公告)号：US09763331B2

公开(公告)日：2017-09-12

申请号：US15066244

申请日：2016-03-10

Applicant: FUJITSU LIMITED

Inventor： Yoshiyuki Hiroshima ,  Naoki Nakamura ,  Akiko Matsui ,  Mitsuhiko Sugane ,  Takahide Mukoyama ,  Tetsuro Yamada ,  Kohei Choraku

IPC: H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/185 ,  H05K1/0216 ,  H05K1/115 ,  H05K1/162 ,  H05K3/306 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09809 ,  H05K2201/10015 ,  H05K2201/10287 ,  H05K2201/10295

Abstract: A printed circuit board includes: a first electrode made of a tubular electric conductor formed on an inner wall of a first hole formed in the printed circuit board; a dielectric body disposed inside the first electrode; and a second electrode made of a tubular electric conductor formed on an inner wall of a second hole extending through the dielectric body, the second electrode having a center axis concentric with the first electrode.

公开(公告)号：US20170221837A1

公开(公告)日：2017-08-03

申请号：US15010868

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brittany L. Hedrick ,  Vijay Sukumaran ,  Christopher L. Tessler ,  Richard F. Indyk ,  Sarah H. Knickerbocker

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H05K3/00 ,  H01L21/56 ,  H05K1/03 ,  H05K1/11 ,  H05K1/02 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/78 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/11 ,  H01L2224/73204 ,  H05K1/0306 ,  H05K3/0026 ,  H05K3/0052 ,  H05K3/0094 ,  H05K2201/0959 ,  H05K2201/10378

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.

公开(公告)号：US09668345B2

公开(公告)日：2017-05-30

申请号：US14389387

申请日：2013-03-27

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Hiroyuki Yamaguchi ,  Seiichi Kurihara ,  Hiroshi Sakurai ,  Shunsuke Nukina

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0154 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2201/10287 ,  H05K2203/061 ,  H05K2203/1572

Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.