公开(公告)号：US20140000949A1

公开(公告)日：2014-01-02

申请号：US13928428

申请日：2013-06-27

Applicant: Hon Hai Precision Industry Co., Ltd.

Inventor： YING-TSO LAI ,  HSIAO-YUN SU

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H05K1/162 ,  H05K2201/09672 ,  H05K2201/09881

Abstract: A capacitor includes a first patterned conductive layer, a second patterned conductive layer and a first patterned dielectric layer. The first patterned conductive layer resembles a comb with internal teeth, and the second patterned conductive layer resembles a comb with external teeth, the internal and the external teeth being interlaced in one plane. A thin first patterned dielectric layer within the same plane is shaped and arranged to infill all the gaps between the teeth. The first patterned conductive layer, the second patterned conductive layer, and the first patterned dielectric layer create a single coplanar layer, and a number of such interconnected coplanar layers are stacked within and contained by a multilayer circuit board.

Abstract translation: 电容器包括第一图案化导电层，第二图案化导电层和第一图案化电介质层。 第一图案化导电层类似于具有内齿的梳子，并且第二图案化导电层类似于具有外齿的梳子，内部和外部齿在一个平面中交织。 同一平面内的薄的第一图案化电介质层被成形和布置以填充齿之间的所有间隙。 第一图案化导电层，第二图案化导电层和第一图案化电介质层产生单个共面层，并且多个这种互连的共面层层叠在多层电路板内并由多层电路板容纳。

公开(公告)号：US20130118779A1

公开(公告)日：2013-05-16

申请号：US13416029

申请日：2012-03-09

Applicant: Duke Kyu LEE ,  Chang Min IM ,  Sang Bum SIM ,  Yun Kee CHO ,  Hyun-Soo JEON

Inventor： Duke Kyu LEE ,  Chang Min IM ,  Sang Bum SIM ,  Yun Kee CHO ,  Hyun-Soo JEON

IPC: H05K1/02 ,  H05K3/22

CPC classification number: H05K1/11 ,  H05K3/22 ,  H05K2201/09881 ,  H05K2203/025

Abstract: A clearance filling PCB includes pin contact units on a surface of the external layer of the PCB and clearance filling units formed by molding a clearance between the pin contact units and polishing an insulating layer so that the height of the insulating layer becomes equal to the height of the pin contact units in order to prevent the sliding of a fine pitch circuit with a pin and induce accurate contact between the fine pitch circuit and the pin, and a method of manufacturing the same. The height of the insulating layer is made equal to the height of the pin contact units by molding the clearance between the pin contact units on the surface of the external layer of the PCB, and the sliding of a fine pitch circuit, requiring contacts, with a pin can be prevented.

Abstract translation: 间隙填充PCB包括在PCB的外层的表面上的销接触单元和通过在引脚接触单元之间模制间隙并抛光绝缘层而形成的间隙填充单元，使得绝缘层的高度等于高度 的引脚接触单元及其制造方法，以防止精细间距电路与引脚的滑动并引起精细间距电路和引脚之间的精确接触。 绝缘层的高度通过模制PCB的外部层的表面上的引脚接触单元之间的间隙和需要触点的细间距电路的滑动而使引脚接触单元的高度等于 可以防止引脚。

公开(公告)号：US20120317805A1

公开(公告)日：2012-12-20

申请号：US13582149

申请日：2011-03-22

Applicant: Jose Antonio Cubero Pitel ,  Andreu Fores Montserrat ,  Maria Leonor Torrijos Ezquerra

Inventor： Jose Antonio Cubero Pitel ,  Andreu Fores Montserrat ,  Maria Leonor Torrijos Ezquerra

IPC: H05K3/10

CPC classification number: H05K3/06 ,  H05K1/09 ,  H05K3/243 ,  H05K2201/0376 ,  H05K2201/09881 ,  Y10T29/49155

Abstract: A method is provided for producing a printed circuit board. The method includes the step of providing an insulating substrate having a layer of aluminum material applied to the substrate. A portion of the layer of aluminum material is removed for defining a circuit trace. A layer of conductive material is applied to the layer of aluminum material.

Abstract translation: 提供了一种用于制造印刷电路板的方法。 该方法包括提供具有施加到基板的铝材料层的绝缘基板的步骤。 去除铝材料层的一部分以限定电路迹线。 将一层导电材料施加到铝材料层上。

公开(公告)号：US08304663B2

公开(公告)日：2012-11-06

申请号：US12155151

申请日：2008-05-30

Applicant: Kohichi Ohsumi

Inventor： Kohichi Ohsumi

IPC: H05K1/16

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/28 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2203/0588 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a wiring board, insulation layers and wiring conductors are alternately laminated, and a plurality of strip-shaped wiring conductors for connecting semiconductor elements are arranged side by side on the outermost insulation layer. Each of the wiring conductors partly has a connection pad to which the electrode terminals of the semiconductor elements are connected by flip-chip bonding. In the wiring board, a solder resist layer is deposited over the outermost insulation layer and the strip-shaped wiring conductors so as to have slit-shaped openings for exposing the upper surfaces of the connection pads. The solder resist layer fills up the space between the connection pads adjacent to each other and exposed within the slit-shaped openings.

Abstract translation: 在布线基板中，绝缘层和布线导体交替层叠，并且多个用于连接半导体元件的条状布线导体并排设置在最外层绝缘层上。 每个布线导体部分地具有连接焊盘，半导体元件的电极端子通过倒装芯片接合连接到该连接焊盘。 在布线板中，在绝缘层和带状布线导体上沉积防焊层，以具有用于暴露连接焊盘上表面的狭缝形开口。 阻焊层填充彼此相邻并在狭缝状开口内露出的连接焊盘之间的空间。

公开(公告)号：US08302297B2

公开(公告)日：2012-11-06

申请号：US12649501

申请日：2009-12-30

Applicant: Kun-Chen Tsai

Inventor： Kun-Chen Tsai

IPC: H01K3/10

CPC classification number: H05K3/205 ,  H01L2924/0002 ,  H05K3/423 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/09563 ,  H05K2201/09881 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.

Abstract translation: 提供一种电路板结构及其制造方法，包括以下步骤：在第一电介质层中形成第一电路层，并从其露出第一电路层; 在所述第一电介质层和所述第一电路层上形成第二电介质层，以及在所述第二电介质层上形成第二电路层; 在第二电介质层中形成多个第一导电通孔，用于电连接到第一电路层，从而省去芯板和电镀孔，从而便于小型化。 此外，第一电介质层在硬化之前是液体，并且形成在增强电路板的层之间的结合的第一电介质层和结构之间。

公开(公告)号：US08186051B2

公开(公告)日：2012-05-29

申请号：US12079785

申请日：2008-03-28

Applicant: Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05K3/02

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.

Abstract translation: 描述了用于制造用于封装衬底和管芯间隔件的层或层的方法。 在一个实施方案中，制造层或层以包括位于平面内的多个陶瓷阱并且由金属通孔隔开，陶瓷井中的凹陷被介电填料材料占据。

公开(公告)号：US08153901B2

公开(公告)日：2012-04-10

申请号：US12092160

申请日：2006-10-30

Applicant: Masayoshi Kondo

Inventor： Masayoshi Kondo

IPC: H05K1/00

CPC classification number: H05K3/4673 ,  H05K3/386 ,  H05K3/4617 ,  H05K3/4626 ,  H05K3/4647 ,  H05K2201/09881 ,  H05K2203/0264 ,  H05K2203/066 ,  H05K2203/1189

Abstract: A multilayer circuit board is fabricated by: preparing a film comprising a first protective film and a first interlayer adhesive; preparing a first circuit board having a first base and a conductive post protruding therefrom; stacking the first interlayer adhesive and the conductive post together; peeling off the first protective film; preparing a second circuit board including a conductive pad receiving the conductive post; and bonding the first circuit board and the second circuit board through the first interlayer adhesive so that the conductive post and the conductive pad face each other, wherein the first interlayer adhesive 104 at the top portion of the conductive post is selectively removed while peeling off the first protective film.

Abstract translation: 多层电路板通过以下步骤制造：制备包括第一保护膜和第一层间粘合剂的膜; 准备具有从其突出的第一基座和导电柱的第一电路板; 将第一层间粘合剂和导电柱堆叠在一起; 剥离第一保护膜; 准备包括接收所述导电柱的导电垫的第二电路板; 以及通过所述第一层间粘合剂将所述第一电路板和所述第二电路板接合，使得所述导电柱和所述导电焊盘彼此面对，其中在所述导电柱的顶部处的所述第一层间粘合剂104被选择性地去除， 第一保护膜。

公开(公告)号：US08147903B2

公开(公告)日：2012-04-03

申请号：US11455865

申请日：2006-06-20

Applicant: Masao Furukawa ,  Yuji Tsuruoka ,  Takashi Mori ,  Nobuhito Yamaguchi ,  Seiichi Kamiya

Inventor： Masao Furukawa ,  Yuji Tsuruoka ,  Takashi Mori ,  Nobuhito Yamaguchi ,  Seiichi Kamiya

IPC: G03F7/00

CPC classification number: H05K3/125 ,  H05K3/245 ,  H05K3/4664 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/1476 ,  Y10S428/901

Abstract: A circuit pattern forming method that can reduce a possibility of undesired short-circuits being produced in the circuit by satellites formed when fabricating a conductive pattern. Thereby, a highly reliable printed circuit board can be formed. A conductive pattern and an insulating pattern of a predetermined thickness are overlappingly drawn by scanning a liquid ejection head and a substrate relative to each other a plurality of times, while ejecting droplets of a conductive pattern forming solution and an insulating pattern forming solution. When forming the conductive pattern and the insulating pattern that adjoin each other on the substrate, the step of forming the insulating pattern of at least one scan is executed between the conductive pattern forming steps that are executed the plurality of times, until the conductive pattern has a predetermined thickness.

Abstract translation: 一种电路图案形成方法，其可以减少当制造导电图案时形成的卫星在电路中产生不期望的短路的可能性。 由此，可以形成高可靠性的印刷电路板。 通过多次扫描液体喷射头和基板，同时喷射导电图案形成溶液和绝缘图案形成溶液的液滴，重叠地绘制具有预定厚度的导电图案和绝缘图案。 当在衬底上形成彼此相邻的导电图案和绝缘图案时，在多次执行的导电图案形成步骤之间执行形成至少一次扫描的绝缘图案的步骤，直到导电图案具有 预定厚度。

公开(公告)号：US20110297424A1

公开(公告)日：2011-12-08

申请号：US13202800

申请日：2010-02-22

Applicant: Hideki Yoshida ,  Satoshi Isoda ,  Naoyuki Urasaki ,  Hayato Kotani

Inventor： Hideki Yoshida ,  Satoshi Isoda ,  Naoyuki Urasaki ,  Hayato Kotani

IPC: H05K1/02 ,  H05K3/02

CPC classification number: G02B5/12 ,  G02F1/133553 ,  G02F1/136286 ,  G02F2203/12 ,  H05K1/0274 ,  H05K3/244 ,  H05K3/28 ,  H05K3/285 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2203/025 ,  Y10T29/49156

Abstract: A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device is mounted; facilitates shaping of the reflection members, controlling of the thickness of the reflection members, and controlling of the surface shape of the reflection members so as to stabilize the reflection rate; and secures close contact between the reflection members and sealing members so as to improve reliability. The wiring board comprises a plurality of wiring layers provided with conductor patterns disposed on base members, and base members which electrically insulate the plurality of wiring layers. At the outermost wiring layer among the plurality of wiring layers, reflection members are formed on the portions of the base member where there are no conductor patterns, the surface of these reflection members and the surface of the conductor patterns are made level and the surface of the conductor patterns are exposed from the reflection members.

Abstract translation: 一种布线板，其使用两个导体图案和设置在其间的间隙的反射构件，以抑制反射率的不均匀性，以提高整体反射率，并且在电子设备的一侧在布线板的表面上提供反射功能 安装; 有助于反射构件的成形，反射构件的厚度的控制，以及反射构件的表面形状的控制以使反射率稳定; 并且确保反射构件和密封构件之间的紧密接触，从而提高可靠性。 布线板包括设置在基底构件上的导体图案的多个布线层和使多个布线层电绝缘的基底构件。 在多个布线层中的最外面布线层处，在不存在导体图形的基底部件上形成有反射部件，这些反射部件的表面和导体图案的表面形成为水平面， 导体图案从反射构件露出。

公开(公告)号：US20110253306A1

公开(公告)日：2011-10-20

申请号：US13169736

申请日：2011-06-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K3/00 ,  B32B38/04

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method of manufacturing a printed circuit board includes the following steps (A) to (D). (A) Laminating a resin insulating layer on each of two sides of a core member to form a core substrate, (B) forming penetrating openings in the core substrate by applying laser beams, (C) forming a rough surface on the core substrate, and (D) providing a metal film for each penetrating opening to form through holes.

Abstract translation: 制造印刷电路板的方法包括以下步骤（A）至（D）。 （A）在芯部件的两侧各自层叠树脂绝缘层，形成芯基板，（B）通过施加激光而在芯基板上形成贯通孔，（C）在芯基板上形成粗糙面， 和（D）为每个穿透孔提供金属膜以形成通孔。