公开(公告)号：US06393696B1

公开(公告)日：2002-05-28

申请号：US09469795

申请日：1999-12-21

Applicant: Kyung-Ro Yoon ,  Keon-Yang Park ,  Byung-Kook Sun

Inventor： Kyung-Ro Yoon ,  Keon-Yang Park ,  Byung-Kook Sun

IPC: H05K336

CPC classification number: H01L23/49833 ,  H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09845 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2924/00014

Abstract: A method for manufacturing a printed circuit board is disclosed. When a metal is plated on an upper board to form a circuit, bonding fingers for being bonded with a semiconductor chip are prevented from being electroplated with a metal. That is, a slot with an ink layer formed therein is formed in each of a plurality of boards. Then window regions of different sizes are defined, and a working is carried out on the portion where the slots are not formed. That is, the copper clad laminates are subjected to a working to form slots, and an ink layer is formed within each of the slots. In this manner, during the plating of the upper face of the printed circuit board, the metal is prevented from intruding into the window region, thereby preventing the formation of a short circuit.

Abstract translation: 公开了一种印刷电路板的制造方法。 当金属镀在上板上以形成电路时，防止与半导体芯片接合的接合指状物被金属电镀。 也就是说，在多个板中的每一个中形成有形成有油墨层的槽。 然后定义不同尺寸的窗口区域，并且在未形成槽的部分进行加工。 也就是说，覆铜层压板经受加工以形成槽，并且在每个槽内形成油墨层。 以这种方式，在印刷电路板的上表面的电镀期间，防止金属进入窗口区域，从而防止形成短路。

公开(公告)号：US06365839B1

公开(公告)日：2002-04-02

申请号：US09587307

申请日：2000-06-05

Applicant: Eric F. Robbins ,  Stephen W. Berry

Inventor： Eric F. Robbins ,  Stephen W. Berry

IPC: H05K103

CPC classification number: H05K1/0253 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09845 ,  H05K2201/09972

Abstract: A multi-layer printed circuit board provides at least two sections thereon. One section has a grouping of high-impedance traces and another adjacent section, separated by a dividing line, has a mainly low-impedance signal traces. The high-impedance section has at least one of a ground and power plane separated from a grouping of central layers, containing the high-impedance traces, by at least one empty or “void” layer. The void layer is likewise filled by the ground and power planes in the within low-impedance section by stepping the ground/power plane inwardly toward the central layers while providing another low-impedance signal trace in the layer above and below the respective ground and power planes. In a preferred embodiment there are at least nine layers of circuit board material with high-impedance traces on a central grouping of at least three central board layers with three layers disposed respectively above and below the central board layers.

Abstract translation: 多层印刷电路板在其上提供至少两个部分。 一个部分具有一组高阻抗迹线，另一个相邻部分由分割线分隔，具有主要的低阻抗信号迹线。 高阻抗部分具有通过至少一个空或“空”层与包含高阻抗迹线的一组中心层分离的接地层和功率平面中的至少一个。 同样，通过将接地/功率平面向内朝向中心层向内侧，通过在内部低阻抗部分内的接地层和电源平面填充空隙层，同时在相应的地面和功率上方和下方的层中提供另外的低阻抗信号迹线 飞机 在一个优选实施例中，至少有九层电路板材料在至少三个中心板层的中心组上具有高阻抗迹线，三层分别设置在中心板层的上方和下方。

公开(公告)号：US20010040048A1

公开(公告)日：2001-11-15

申请号：US09812989

申请日：2001-03-20

Inventor： Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy ,  Andrew Zachary Glovatsky ,  Robert Edward Belke ,  Robert Joseph Gordon ,  Thomas Bernd Krautheim

IPC: H05K001/03

CPC classification number: H05K3/4685 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10, 110 for making multi-layer electronic circuit boards 82, 148 having metallized apertures 18, 20, 118, 120 which may be selectively and electrically connected to a source of ground potential.

Abstract translation: 一种用于制造具有金属化孔18,20,118,120的多层电子电路板82,148的方法10,110，其可以选择性地和电连接到地电位源。

公开(公告)号：US20010036064A1

公开(公告)日：2001-11-01

申请号：US09814486

申请日：2001-03-20

Inventor： Delin Li

IPC: H05K007/02

CPC classification number: H05K3/4685 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10 for making a multi-layer electronic circuit board 110 having electroplated apertures 18, 20 which may be selectively and electrically isolated from electrically grounded member 12 and further having selectively formed air bridges and/or crossover members 50 which are structurally supported by material 54, and further having certain exposed connection surfaces 112, selectively and electrically connected to certain electrically conductive members 34, 42, and 44.

Abstract translation: 一种用于制造具有电镀孔18,20的多层电子电路板110的方法10，其可以与电接地构件12选择性地和电隔离，并且还具有结构上由材料支撑的选择性地形成的空气桥和/或交叉构件50 并且还具有某些暴露的连接表面112，其选择性地和电连接到某些导电构件34,42和44。

公开(公告)号：US20010035570A1

公开(公告)日：2001-11-01

申请号：US09488087

申请日：2000-01-20

Inventor： Takahiro Iijima ,  Akio Rokugawa

IPC: H01L023/02

CPC classification number: H05K1/114 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09845 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers; wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.

Abstract translation: 一种用于半导体器件的封装，包括：芯板，其具有形成在其上的前侧基部布线图案的正面和形成在其上的背面基底布线图案的背面，所述前侧布线图案和所述背面布线图案彼此电连接 通过穿透核心板的导体段; 上侧布线图案与前侧基布线图案之间介于其间的中间绝缘层的上侧布线图案的前侧层压体，其中每个相邻的一对上布线图案通过贯通孔的侧壁上的通孔镀层彼此电连接 介于相邻对之间的中间绝缘层之一，其中最上面的一个上布线图案被图案化以与半导体芯片电连接; 背面基底布线图案上的绝缘层的背面层叠体; 绝缘层的背面叠层体上具有外部连接端子的外部连接布线图案; 其中所述外部连接布线图案通过穿过绝缘层的背面层叠体的通孔电连接到所述背面基底布线图案。

公开(公告)号：US20010032388A1

公开(公告)日：2001-10-25

申请号：US09885851

申请日：2001-06-20

Inventor： Terrel L. Morris

IPC: H01K003/10 ,  B23B039/00 ,  H05K003/02

CPC classification number: H05K3/3421 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09845 ,  H05K2201/10704 ,  H05K2203/0455 ,  Y02P70/613 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention relates to the production of an improved via for attaching electrical connection pins to printed circuit boards. The inventive via provides a connection having robust mechanical attachment and minimal capacitance effects. The via provides a wide diameter for accepting an electrical connection pin and a reduced diameter along other portions of the length of the via for reduced capacitance and reduced electrical discontinuity.

Abstract translation: 本发明涉及一种用于将电连接引脚连接到印刷电路板的改进的通孔的制造。 本发明的通孔提供具有坚固的机械附接和最小的电容效应的连接。 通孔提供宽直径，用于接受电连接销，并且沿着通孔长度的其他部分减小直径，以减小电容量并减小电气不连续性。

公开(公告)号：US06300566B1

公开(公告)日：2001-10-09

申请号：US09412074

申请日：1999-10-04

Applicant: Ulf Scheuerer ,  Frank Franzen ,  Christian Fritzsche

Inventor： Ulf Scheuerer ,  Frank Franzen ,  Christian Fritzsche

IPC: H05K506

CPC classification number: H01R12/62 ,  H01R4/04 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/281 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0367 ,  H05K2201/09845

Abstract: An electrical connection configuration connects a circuit carrier to conductor tracks of a conductor-track carrier. Both the circuit carrier and the conductor-track carrier are carried by a base plate. The circuit carrier and the conductor-track carrier have a region in which they overlap and in which they are connected by an electrically conductive adhesive.

Abstract translation: 电连接配置将电路载体连接到导体轨道载体的导体轨道。 电路载体和导体轨道载体都由基板承载。 电路载体和导体轨道载体具有它们重叠的区域，并且它们通过导电粘合剂连接。

公开(公告)号：US06252176B1

公开(公告)日：2001-06-26

申请号：US08839253

申请日：1997-04-17

Applicant: Munehiro Kuramochi ,  Hiroshi Hagiwara ,  Kouichi Maeyama

Inventor： Munehiro Kuramochi ,  Hiroshi Hagiwara ,  Kouichi Maeyama

IPC: H05K346

CPC classification number: H05K3/4655 ,  H05K1/024 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/063

Abstract: A printed wiring board includes an insulating layer, conductive layers respectively formed into predetermined circuit patterns on the upper and lower surfaces of at least the insulating layer, and a conducting section formed in a portion of the insulating layer so as to enable electrical connection between the upper and lower conductive layers. A thickness of the insulating layer is varied to change the electric characteristics of the printed wiring board according to a circuit configuration of the conductive layers.

Abstract translation: 印刷布线板包括绝缘层，至少绝缘层的上表面和下表面上分别形成为预定电路图形的导电层，以及形成在绝缘层的一部分中的导电部分，以使得能够在 上下导电层。 根据导电层的电路结构，改变绝缘层的厚度以改变印刷电路板的电特性。

公开(公告)号：US06194990B1

公开(公告)日：2001-02-27

申请号：US09268956

申请日：1999-03-16

Applicant: Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

Inventor： Tien Lee ,  Lawrence Lach ,  Gregory J. Dunn

IPC: H01C101

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

Abstract translation: 适用于多层印刷电路板（12）的薄膜金属电阻（44）及其制造方法。 电阻器（44）通常具有多层结构，其中电阻器（44）的各个层（34,38）彼此自对准，使得产生负的互感，其几乎抵消了自感 的每个电阻层（34,38）。 结果，电阻器（44）具有非常低的净寄生电感。 此外，电阻器（44）的多层结构减小了容纳电阻器（44）所需的电路板（12）的面积，结果减少了与其他层上的其它电路元件的寄生相互作用的问题 电路板（12）。

公开(公告)号：US6114240A

公开(公告)日：2000-09-05

申请号：US250289

申请日：1999-02-12

Applicant: Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood

IPC: H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H01L21/44

CPC classification number: H05K1/112 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/16237 ,  H01L2224/82039 ,  H01L2225/1005 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0306 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K3/0029 ,  H05K3/0032

Abstract: A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts on the component, using a laser beam that is focused to produce a desired via geometry. The vias can include enlarged end portions to facilitate deposition of a conductive material during formation of the vias, and to provide an increased surface area for forming the contacts. For example, by focusing the laser beam at a midpoint of a substrate of the component, an hour glass via geometry is provided. Alternately, the laser beam can be focused at an exit point, or at an entry point of the substrate, to provide converging or diverging via geometries. The method can also include forming contact pins on the conductive vias by bonding and shaping metal wires using a wire bonding process, or a welding process.

Abstract translation: 提供了一种制造诸如封装，互连和测试载体的半导体部件的方法。 该方法包括激光加工用于使部件上的触点互连的导电通孔，使用聚焦以产生所需通孔几何形状的激光束。 通孔可以包括扩大的端部，以便于在形成通孔期间沉积导电材料，并且提供用于形成触点的增加的表面积。 例如，通过将激光束聚焦在部件的基板的中点处，提供了小时玻璃通孔几何形状。 或者，激光束可以在出口点处或在基板的入口处聚焦，以提供会聚或发散的几何形状。 该方法还可以包括通过使用引线接合工艺或焊接工艺接合和成形金属线来在导电通孔上形成接触引脚。