公开(公告)号：US4689103A

公开(公告)日：1987-08-25

申请号：US798871

申请日：1985-11-18

Applicant: Vito D. Elarde

Inventor： Vito D. Elarde

IPC: H05K3/00 ,  H05K3/10 ,  B29C45/03

CPC classification number: H05K3/107 ,  H05K3/0097 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2203/0165 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A plurality of physically separate plastic substates are injection molded, each with at least one pattern of channels formed in a surface of thereof defining a conductive circuit to be formed. The plurality of substrates are then physically connected in a common planar array either by inserting them in corresponding receptacles in a carrier board, by mating peripheral connecting elements, by using adhesive or by some other suitable connecting mechanism. Where a carrier board with pre-formed receptacles is not utilized, the individual substrates in the array are pierced and replaced. The planar array is processed to simultaneously form a conductive circuit on each substrate consisting of metal deposited in its pattern of channels. The planar array of metallized substrates may then be stuffed with electronic components on an automatic insertion machine, wave soldered. The individual finished circuit boards are then pressed out. This batch processing results in substantial savings in handling costs and avoids the significant expense and tolerance problems associated with using very large molds which would be required to form the large planar array directly.

Abstract translation: 多个物理上分离的塑料子状态是注射成型的，每个具有形成在其表面中的限定要形成的导电电路的通道中的至少一个图案。 然后通过使用粘合剂或通过一些其它合适的连接机构将多个基板通过将它们插入到载体板中的相应的容器中，通过配合外围连接元件来物理地连接在共同的平面阵列中。 在没有使用带有预成型插座的承载板的情况下，阵列中的各个基板被穿孔并更换。 处理平面阵列以在由以其通道图案沉积的金属组成的每个基板上同时形成导电电路。 然后，金属化基板的平面阵列可以在自动插入机上填充电子部件，波形焊接。 然后将各个成品电路板压出。 这种批量处理可大大节省处理成本，并避免与使用直接形成大平面阵列所需的非常大的模具相关的显着的费用和公差问题。

公开(公告)号：US4572764A

公开(公告)日：1986-02-25

申请号：US681189

申请日：1984-12-13

Applicant: Roxy N. Fan

Inventor： Roxy N. Fan

IPC: H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/46 ,  B44C1/22 ,  B05D5/12 ,  G03C5/00

CPC classification number: H05K3/0023 ,  H05K3/184 ,  H05K3/4661 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2203/0525 ,  H05K2203/072 ,  H05K2203/1415 ,  H05K3/102 ,  H05K3/246 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: Process for preparing multilayer printed circuits comprising laminating to a substrate bearing a circuit pattern or electrically conductive surface a photosensitive layer which is tacky or becomes tacky upon exposure; exposing the laminate to actinic radiation through a via image related to the underlying circuit pattern, if present; optionally removing the removable via image of the photosensitive layer in either the exposed or unexposed areas, e.g., with a solvent or peeling apart by removal of a cover sheet, if present; laminating to the remaining tacky photosensitive layer a layer of a second photosensitive composition; exposing the laminate to actinic radiation through a registered image pattern of at least one overlying segment of the via image area and conductive circuit pattern to form an image surface having nontacky areas and removable circuit image areas; removing the removable circuit image areas of the photosensitive layer in the exposed or unexposed areas with a solvent therefor, or peeling apart by means of a cover sheet, if present, the removable via image areas of the lower photosensitive, if present, are removed by a solvent therefor; embedding finely divided material, e.g., copper, into the tacky areas; optionally curing the laminate by means of actinic radiation and/or heat; plating electrolessly to form an interconnected electrically conductive circuit. Additional circuit layers can be added.

Abstract translation: 制备多层印刷电路的方法包括层压到承载电路图形或导电表面的基底上，所述光敏层在曝光时发粘或变粘， 通过与底层电路图案相关的通孔图像将层压体暴露于光化辐射（如果存在） 任选地在暴露或未曝光的区域（例如用溶剂）中去除感光层的可移除通孔图像，或者通过去除覆盖片（如果存在）剥离; 将第二感光组合物的层层压到剩余的粘性感光层上; 通过所述通孔图像区域和导电电路图案的至少一个覆盖段的注册图像图案将所述层压体暴露于光化辐射，以形成具有非粘性区域和可移除电路图像区域的图像表面; 通过其溶剂去除曝光或未曝光区域中的感光层的可移除电路图像区域，或者通过覆盖片剥离（如果存在），可以通过下部光敏剂的可移除通孔图像区域（如果存在的话）被 其溶剂; 将细碎的材料例如铜嵌入粘性区域中; 任选地通过光化辐射和/或加热固化层压体; 电化学镀以形成互连的导电电路。 可以添加额外的电路层。

公开(公告)号：US4556628A

公开(公告)日：1985-12-03

申请号：US600063

申请日：1984-04-13

Applicant: Johann Greschner ,  Friedrich W. Schwerdt ,  Hans J. Trumpp

Inventor： Johann Greschner ,  Friedrich W. Schwerdt ,  Hans J. Trumpp

IPC: H05K3/42 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/10 ,  H05K3/16 ,  H05K3/24 ,  H05K3/40 ,  G03C5/00

CPC classification number: H05K3/0041 ,  H05K3/048 ,  H05K3/107 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0554 ,  H05K2203/0585 ,  H05K2203/072 ,  H05K2203/095 ,  H05K3/108 ,  H05K3/16 ,  H05K3/244 ,  H05K3/426

Abstract: A process for producing printed circuit boards having metallic conductor structures embedded in the insulating substrate and whose front and back sides are conductively connected by means of plated through holes. The first steps of the process comprise producing a matrix on an epoxy resin substrate consisting of a lift-off layer, an aluminum barrier layer and a positive photoresist layer. A negative image of the desired conductor pattern is then generated in the photoresist layer using conventional photolithographic techniques. The negative image is etched into the barrier layer and the lift-off layer such that an undercut occurs under the barrier layer. Subsequently, vertical trenches are etched into the epoxy resin substrate. After drilling of the through holes, an activating layer of copper is deposited by means of magnetic field enhanced cathode sputtering on the surfaces of the trenches, the through holes and the barrier layer. The lift-off layer, together with the barrier layer covering it, is removed by immersion in a suitable solvent, and copper conductors are subsequently grown in the etched conductor trenches.

Abstract translation: 一种用于制造印刷电路板的方法，该印刷电路板具有嵌入绝缘基板中的金属导体结构，其前侧和后侧通过电镀通孔导电连接。 该方法的第一步包括在由剥离层，铝阻挡层和正性光致抗蚀剂层组成的环氧树脂基材上制备基质。 然后使用常规光刻技术在光致抗蚀剂层中产生所需导体图案的负像。 负像被蚀刻到阻挡层和剥离层中，使得在阻挡层下方发生底切。 随后，将垂直沟槽蚀刻到环氧树脂基板中。 在通孔钻孔之后，通过磁场强化阴极溅射在沟槽，通孔和阻挡层的表面上沉积铜的激活层。 剥离层与覆盖它的阻挡层一起通过浸入合适的溶剂中除去，然后在蚀刻的导体沟槽中生长铜导体。

公开(公告)号：US4463084A

公开(公告)日：1984-07-31

申请号：US430601

申请日：1982-09-30

Applicant: Ken'ichi Mitsumori ,  Kazuo Aikawa

Inventor： Ken'ichi Mitsumori ,  Kazuo Aikawa

IPC: H05K1/03 ,  H05K1/05 ,  H05K3/06 ,  H05K3/10 ,  H05K3/44 ,  G03C5/00

CPC classification number: H05K1/053 ,  H05K3/44 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0323 ,  H05K2203/1147 ,  H05K3/06 ,  H05K3/107

Abstract: A circuit board such as a code disk having a smooth contact surface and a minute pattern is fabricated by depositing an alumite film on an aluminum and selectively filling electrically nonconductive and conductive materials in the cells in the crystals of the alumite film.

Abstract translation: 通过在铝上沉积耐酸铝膜并选择性地填充耐酸铝膜的晶体中的电池中的非导电和导电材料来制造诸如具有光滑接触表面和微小图案的代码盘的电路板。

公开(公告)号：US4339305A

公开(公告)日：1982-07-13

申请号：US231712

申请日：1981-02-05

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: H01F41/34 ,  H01L21/48 ,  H05K1/03 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/4846 ,  H01F41/34 ,  H05K3/107 ,  H05K1/0306 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/072 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/048 ,  H05K3/244 ,  H05K3/4661

Abstract: The method of manufacturing predetermined microcircuit conductor patterns, which includes forming on the surface plane of a substrate a layer of insulator material, forming a layer of resist on the layer of insulator material, patterning the layer of resist to define a channel pattern, etching the channel pattern with relatively overwide channels, conditioning the channel bases to receive plating material, and thereafter filling the overwide channels with the plating material to a height at least substantially co-planar with the insulator material to define the predetermined conductor patterns, removing the mask and plated material thereon to uncover completely the conductor pattern.

Abstract translation: 制造预定微电路导体图案的方法包括在绝缘体材料层上形成绝缘体材料层，在绝缘体材料层上形成抗蚀剂层，图案化抗蚀剂层以限定沟道图案，蚀刻 通道图案具有相对超范围的通道，调节通道基底以接收电镀材料，然后用电镀材料填充超宽通道至与绝缘体材料至少基本共面的高度，以限定预定导体图案，去除掩模和 在其上镀覆材料以完全揭露导体图案。

公开(公告)号：US3926763A

公开(公告)日：1975-12-16

申请号：US31102272

申请日：1972-11-30

Applicant: IBM

Inventor： REISMAN ARNOLD

IPC: H01J17/49 ,  H05K1/00 ,  H05K1/03 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/14 ,  C23C15/00 ,  B44D1/18

CPC classification number: H01J11/00 ,  H05K1/0289 ,  H05K1/0306 ,  H05K3/002 ,  H05K3/048 ,  H05K3/107 ,  H05K3/143 ,  H05K2201/0376 ,  H05K2201/09036

Abstract: An improved glass panel gas discharge display structure wherein a photolithography step on a plate forming the glass panel is used before metallizing the plate through a mask so that when subsequent dissolution of the mask takes place, the plate is left with embedded metallization essentially coplanar with the surface. The effects of such an embedded electrode structure are that it minimizes attack of the metallization when flow on dielectrics are applied since the sidewalls of the electrodes are protected; it permits application of very thin dielectrics by flow-on, sputtering, plasma spraying, evaporation or other suitable techniques since problems of overcoating around edges are eliminated. It minimizes stresses in the composite structure overlying the substrate support and it minimizes adjacent line interactions when very thin coatings are applied. It also minimizes surface irregularities on panel plates.

公开(公告)号：US3873429A

公开(公告)日：1975-03-25

申请号：US37788473

申请日：1973-07-09

Applicant: ROCKWELL INTERNATIONAL CORP

Inventor： BROWN ELVIN E

IPC: H05K1/11 ,  H05K3/42 ,  C23B5/48

CPC classification number: H05K1/116 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2203/0278 ,  H05K2203/0542

Abstract: A process for producing flush printed circuits with plated through holes comprising etching the circuit paths, flushing the circuit paths with the surface of the material, drilling the holes and producing plating material in the hole area through and subsequent to the use of electroless flash material and then removing the flash from all areas other than the hole portion of the circuit board.

Abstract translation: 一种用于制造具有电镀通孔的冲压印刷电路的方法，包括蚀刻电路路径，用材料的表面冲洗电路路径，钻孔并在孔区域中通过使用无电闪光材料产生电镀材料， 然后从电路板的孔部以外的所有区域除去闪光。

公开(公告)号：USB437450I5

公开(公告)日：1975-01-28

申请号：US43745074

申请日：1974-01-28

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46

CPC classification number: H05K3/465 ,  H05K1/0219 ,  H05K1/0221 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/4661 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2201/09809 ,  H05K2203/0733

公开(公告)号：US3675095A

公开(公告)日：1972-07-04

申请号：US3675095D

申请日：1971-06-10

Applicant: RCA CORP

Inventor： LEHMANN WILLIAM LESTER

IPC: H01G2/06 ,  H05K1/16 ,  H01G1/035

CPC classification number: H01G2/06 ,  H05K1/162 ,  H05K2201/0376 ,  H05K2201/09236

Abstract: An improved printed capacitor includes a pair of inner and outer, closely spaced, coplanar electrodes. The inner electrode has the general shape of a cross, and the outer electrode surrounds the inner electrode and also has the general shape of a cross. The capacitor has a substantially constant capacitance regardless of the relative position of the inner electrode with respect to the outer electrode.

Abstract translation: 改进的印刷电容器包括一对内部和外部紧密间隔的共面电极。 内部电极具有十字形的一般形状，外部电极围绕内部电极并且具有十字形的大致形状。 无论内部电极相对于外部电极的相对位置如何，电容器具有基本恒定的电容。

公开(公告)号：US3496073A

公开(公告)日：1970-02-17

申请号：US3496073D

申请日：1967-03-02

Applicant: HOLLANDSE NV

Inventor： ROY DICK LA

IPC: C25D5/02 ,  C25D5/44 ,  C25D7/00 ,  C25D11/12 ,  G03F7/00 ,  H01H1/02 ,  H01H1/021 ,  H01H19/58 ,  H05K1/05 ,  H05K1/09 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/44 ,  C23B5/50 ,  C23B5/08 ,  C23B5/28

CPC classification number: H01H19/585 ,  C25D5/02 ,  C25D5/44 ,  C25D7/00 ,  C25D11/12 ,  G03F7/00 ,  H01H1/02 ,  H01H1/021 ,  H05K1/05 ,  H05K1/053 ,  H05K1/09 ,  H05K3/002 ,  H05K3/107 ,  H05K3/184 ,  H05K3/243 ,  H05K3/44 ,  H05K2201/0376 ,  H05K2201/09554 ,  H05K2203/0315