公开(公告)号：US20170236725A1

公开(公告)日：2017-08-17

申请号：US15466063

申请日：2017-03-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

公开(公告)号：US09713267B2

公开(公告)日：2017-07-18

申请号：US14674301

申请日：2015-03-31

Applicant: IBIDEN CO., LTD.

Inventor： Toru Furuta ,  Takeshi Furusawa ,  Tomoya Terakura

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/02 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/0097 ,  H05K3/282 ,  H05K3/3436 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09745 ,  H05K2201/09772 ,  H05K2203/0369 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/49165

Abstract: A method for manufacturing a printed wiring board with conductive posts includes forming on a first foil provided on carrier a first conductive layer including mounting pattern to connect electronic component via conductive posts, forming on the first foil a laminate including an insulating layer and a second foil to form the laminate on the first conductive layer, removing the carrier, forming a metal film on the laminate and first film, forming resist on the metal film to have pattern exposing portion of the metal film corresponding to the mounting pattern and portion of the second foil for a second conductive layer, forming an electroplating layer on the portion of the metal film not covered by the resist, removing the resist, and applying etching to remove the first and second foils below the metal film exposed by the removing the resist and to form the posts on the mounting pattern.

公开(公告)号：US09704795B2

公开(公告)日：2017-07-11

申请号：US14820963

申请日：2015-08-07

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Kota Noda

IPC: H01L23/49 ,  H01L21/48 ,  H05K1/02 ,  H05K3/40 ,  H01L23/498 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0278 ,  H05K1/111 ,  H05K3/4015 ,  H05K2201/0376 ,  H05K2201/09827 ,  H01L2924/00

Abstract: A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings.

公开(公告)号：US20170194241A1

公开(公告)日：2017-07-06

申请号：US15461499

申请日：2017-03-17

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

公开(公告)号：US09668341B2

公开(公告)日：2017-05-30

申请号：US15158777

申请日：2016-05-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Jun Furuichi ,  Noriyoshi Shimizu

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/0191 ,  H05K2201/0376 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2203/025

Abstract: A wiring substrate includes a core layer having a penetrating hole, a first insulating layer disposed on a first surface of the core layer and having a first opening at a position of the penetrating hole, the first insulating layer containing no filler, a penetrating electrode disposed in the penetrating hole and in the first opening, and a first wiring layer laminated both on the first insulating layer at a first surface thereof facing away from the core layer and on an end face of the penetrating electrode, wherein the first surface of the first insulating layer and the end face of the penetrating electrode are planarized.

公开(公告)号：US20170077045A1

公开(公告)日：2017-03-16

申请号：US15364185

申请日：2016-11-29

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/35121 ,  H05K1/0373 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014

Abstract: A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.

Abstract translation: 半导体结构包括绝缘层，多个阶梯形导电通孔和图案化电路层。 绝缘层包括顶表面和与顶表面相对的底表面。 阶梯状导电通孔设置在绝缘层处以电连接顶表面和底表面。 每个阶梯式导电通孔包括头部和连接到头部的颈部。 头部设置在顶表面上，头部的上表面与顶表面共面。 头部的最小直径大于颈部的最大直径。 图案化电路层设置在顶表面上并电连接到阶梯式导电通孔。

公开(公告)号：US20170032978A1

公开(公告)日：2017-02-02

申请号：US15218466

申请日：2016-07-25

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Terumasa Moriyama ,  Tomota Nagaura

IPC: H01L21/48 ,  H05K3/46

CPC classification number: H01L21/4857 ,  C25D1/04 ,  C25D3/18 ,  C25D3/38 ,  C25D3/562 ,  C25D3/58 ,  C25D5/022 ,  C25D5/10 ,  C25D9/08 ,  H01L21/486 ,  H01L23/49866 ,  H05K3/025 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/421 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/0726 ,  Y10T428/12431 ,  Y10T428/12438 ,  Y10T428/12472

Abstract: A carrier-attached copper foil having good circuit formability is provided. The carrier-attached copper foil has a carrier, an intermediate layer and an ultra-thin copper layer in this order, the average grain size of crystal grains that form the ultra-thin copper layer is 1.05 to 6.5 μm, and a ten point average roughness Rz of a surface on a side of the ultra-thin copper layer is 0.1 to 2.0 μm.

Abstract translation: 提供具有良好电路成形性的载体附着铜箔。 载体附着铜箔依次具有载体，中间层和超薄铜层，形成超薄铜层的晶粒的平均粒径为1.05〜6.5μm，十点平均 超薄铜层侧表面的粗糙度Rz为0.1〜2.0μm。

公开(公告)号：US20170009975A1

公开(公告)日：2017-01-12

申请号：US15153053

申请日：2016-05-12

Applicant: LG ELECTRONICS INC.

Inventor： Jaepyo HONG ,  Jaechan KIM ,  Injoong KIM ,  Hyeuk CHANG ,  Sumin JUN

IPC: F21V29/74

CPC classification number: F21V29/74 ,  F21Y2101/00 ,  H01L33/62 ,  H01L33/64 ,  H01L33/647 ,  H05K1/053 ,  H05K3/28 ,  H05K2201/0376 ,  H05K2201/10106 ,  H05K2201/2054 ,  H05K2203/1355

Abstract: A light source module includes at least one light source, and a body supporting the light source. The body includes a heat sink supporting the light source on a top surface thereof, the heat sink absorbing heat from the light source and dissipating the heat to the outside, an insulating layer provided on at least one surface of the heat sink, the insulating layer having electrical insulating properties, and a conductive layer provided on the insulating layer. The conductive layer includes connection regions through which electric current is supplied to the light source, and a light source region disposed between the connection regions, the light source region having the light source mounted therein. A protective layer is stacked in the connection region. Accordingly, it is possible to obtain effects such as rapid fabrication processes, inexpensive fabrication cost, facilitation of mass production, improvement of product yield, protection of a conductive material, improvement of the lifespan of products, and enhancement of the stability of products.

Abstract translation: 光源模块包括至少一个光源和支撑光源的主体。 本体包括在其顶表面上支撑光源的散热器，散热片吸收来自光源的热量并将热量散发到外部，设置在散热器的至少一个表面上的绝缘层，绝缘层 具有电绝缘性，以及设置在绝缘层上的导电层。 导电层包括通过其向电源供应电流的连接区域和设置在连接区域之间的光源区域，其中安装有光源的光源区域。 保护层层叠在连接区域中。 因此，可以获得快速制造工艺，廉价的制造成本，便于大量生产，提高产品产量，保护导电材料，提高产品寿命以及提高产品稳定性等效果。

公开(公告)号：US20160381793A1

公开(公告)日：2016-12-29

申请号：US15189255

申请日：2016-06-22

Applicant: KYOCERA Corporation

Inventor： Masaharu YASUDA ,  Yoshihiro HASEGAWA

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4682 ,  H05K3/0097 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2201/2072 ,  H05K2203/1536

Abstract: A wiring board of the present disclosure includes an insulating layer and a wiring conductor. The wiring conductor is buried in an insulating layer in such a manner as to have a top surface exposed to a surface of the insulating layer. The wiring conductor includes, at a portion buried in the insulating layer, a wiring level difference part or a wiring inclined part having a width larger than a width of the top surface.

Abstract translation: 本公开的布线板包括绝缘层和布线导体。 布线导体以使顶表面暴露于绝缘层的表面的方式埋在绝缘层中。 布线导体包括在绝缘层中埋设的部分的布线级差部分或具有比顶表面的宽度大的宽度的布线倾斜部分。

公开(公告)号：US09474149B2

公开(公告)日：2016-10-18

申请号：US14443231

申请日：2013-11-15

Applicant: JUMATECH GMBH

Inventor： Markus Wölfel

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/20

CPC classification number: H05K1/028 ,  H05K1/0265 ,  H05K1/0278 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/0017 ,  H05K3/202 ,  H05K2201/0275 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/057 ,  H05K2201/09027 ,  H05K2201/0969 ,  H05K2201/1028 ,  Y10T29/49156

Abstract: The invention relates to an angle-adjustable and/or printed circuit board structure having at least two printed circuit board sections arrangeable or arranged angularly with respect to one another, wherein the printed circuit board structure contains at least one conduction element which is embedded at least predominantly in the printed circuit board structure and which extends between two contact pads and is electrically conductively connected to said contact pads, wherein the two contact pads are situated on different printed circuit board sections, wherein the printed circuit board sections are angle-adjustable and/or angled relative to one another with maintenance of the connections between the contact pads and the at least one conduction element and with bending of the at least one conduction element via a bending edge between the printed circuit board sections. In order to improve the electrical and mechanical connection between the printed circuit board sections, the invention provides for the conduction element to have a larger extent along the bending edge than perpendicularly thereto, as viewed in cross section. A corresponding method for producing this printed circuit board structure is like wise claimed.

Abstract translation: 本发明涉及一种角度可调节和/或印刷电路板结构，其具有至少两个相对于彼此成角度布置或布置的印刷电路板部分，其中印刷电路板结构包含至少一个传导元件，其至少嵌入 主要在印刷电路板结构中并且在两个接触焊盘之间延伸并且导电地连接到所述接触焊盘，其中两个接触焊盘位于不同的印刷电路板部分上，其中印刷电路板部分是角度可调节的和/ 或相对于彼此成角度，同时维持接触焊盘和至少一个导电元件之间的连接，并且经由印刷电路板部分之间的弯曲边缘弯曲至少一个导电元件。 为了改善印刷电路板部分之间的电气和机械连接，本发明提供了导电元件沿着弯曲边缘比垂直于其更大的程度，如横截面所示。 用于制造该印刷电路板结构的相应方法如所示。