公开(公告)号：US06734553B2

公开(公告)日：2004-05-11

申请号：US10151416

申请日：2002-05-20

Applicant: Naoto Kimura

Inventor： Naoto Kimura

IPC: H01L2334

CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/021 ,  H05K1/144 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: The semiconductor device according to the present invention is equipped with a plurality of electronic circuits including at least one semiconductor integrated circuit chip, and a plurality of intermediate substrates interposed between the electronic components and a package and mounting the electronic components directly on its one major face, where each of the electronic component has on the one major face at least a plurality of first electrodes connected to the electronic components, a plurality of second electrodes for external connection, and internal connection electrodes for connecting between the electronic components including the connection between the first electrodes and the second electrodes that are mutually corresponding.

公开(公告)号：US20040078967A1

公开(公告)日：2004-04-29

申请号：US10689471

申请日：2003-10-20

Inventor： Tongbi Jiang ,  Edward A. Schrock

IPC: H01R013/432 ,  H01R009/00 ,  H05K003/34

CPC classification number: H01L24/83 ,  H01L24/31 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/095 ,  H05K3/1216 ,  H05K3/4007 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2203/167 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49181 ,  Y10T29/49204 ,  H01L2924/00

Abstract: A Z-axis electrical contact may be formed using a resinous deposit containing conductive particles which may align along surface regions to form an electrical conduction path over the resinous material. If the resinous material is thermoplastic, the material may be heated to mechanically bond to contact surfaces. Advantageously, the resinous material may be formed by forcing a resinous matrix containing conductive particles through an annular opening in a stencil. The resulting member allows surfaces to be contacted which may be irregular or may be covered by native oxide layers.

Abstract translation: 可以使用含有导电颗粒的树脂沉积物形成Z轴电接触，所述导电颗粒可以沿着表面区域排列以在树脂材料上形成电传导路径。 如果树脂材料是热塑性的，则材料可以被加热以机械地结合到接触表面。 有利地，树脂材料可以通过强制含有导电颗粒的树脂基质通过模板中的环形开口形成。 所得到的构件允许接触表面，其可以是不规则的或可以被天然氧化物层覆盖。

公开(公告)号：US06720500B1

公开(公告)日：2004-04-13

申请号：US09042989

申请日：1998-03-17

Applicant: Masajiro Inoue

Inventor： Masajiro Inoue

IPC: H05K710

CPC classification number: H01R13/2414 ,  H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01063 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15312 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/0064 ,  H05K3/28 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09909 ,  H05K2201/10303 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10704 ,  Y10T29/4913 ,  Y10T29/49147 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/05442 ,  H01L2224/05599

Abstract: A plug-in type electronic control unit is comprised of a wiring board, a plurality of electronic parts mounted on one surface of the wiring board by utilizing a wireless bonding process, and a plug member mounted on the other surface of the wiring board by utilizing a wireless bonding process. It is possible to suppress the planar extent of the unit by such a laminated structure, and to suppress the extent of the unit in a laminating direction by the employment of the wireless bonding process. Thus, it is possible to achieve a reduction in size of the plug-in type electronic control unit.

Abstract translation: 插电式电子控制单元由布线板，通过利用无线接合工艺安装在布线板的一个表面上的多个电子部件和通过利用布线板安装在布线板的另一个表面上的插塞构件 无线绑定过程。 通过这样的层叠结构，可以抑制单位的平面化程度，并且通过使用无线接合处理来抑制单元在层叠方向上的程度。 因此，可以实现插入式电子控制单元的尺寸的减小。

公开(公告)号：US20040060174A1

公开(公告)日：2004-04-01

申请号：US10661530

申请日：2003-09-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Kei Imafuji ,  Tadashi Kodaira ,  Takeshi Chino ,  Jyunichi Nakamura ,  Miwa Abe

IPC: H05K003/36

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49816 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0338 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method for producing a wiring substrate provided with bumps protruding from a surface of the substrate, the method comprising the steps of: covering one side of a metallic base with an electrical insulating film and forming open holes in the insulating film so as to expose at the bottoms thereof the base, etching the base using the insulating film having the open holes formed as a mask to form concavities in the base, electroplating the interior face of each of the concavities using the base as a plating power supply layer to form a barrier metal film on the interior face of each concavities, filling the concavities with a material for the bump by electroplating using the base as a plating power supply layer, forming a barrier layer on the surface of the material for the bump filled in each of the concavities using the base as a plating power supply layer, forming a stack of a predetermined number of wiring patterns on the insulating film, the adjacent wiring patterns in the stack being separated from each other by an intervening insulating layer and being connected to each other through vias formed in the intervening insulating layer, and the wiring patterns being electrically connected to the material for the bump filled in the concavities, removing the base from the stack of wiring patterns having bumps each having the barrier metal film, and removing the barrier metal film from each of the bumps.

Abstract translation: 一种制造布线基板的方法，所述布线基板设置有从所述基板的表面突出的凸起，所述方法包括以下步骤：用电绝缘膜覆盖金属基底的一侧并在所述绝缘膜中形成露出孔，以暴露在 其底部使用具有形成为掩模的开孔的绝缘膜蚀刻基底，以在基底中形成凹部，使用基底电镀每个凹部的内表面作为电镀电源层以形成屏障 在每个凹部的内表面上的金属膜，通过使用基底作为电镀电源层的电镀将用于凸块的材料填充凹部，在填充在每个凹部中的凸块材料的表面上形成阻挡层 使用基底作为电镀电源层，在绝缘膜上形成预定数量的布线图案的叠层，堆叠中的相邻布线图案 通过中间绝缘层彼此分离并且通过形成在中间绝缘层中的通孔彼此连接，并且布线图案电连接到填充在凹部中的用于凸块的材料，从堆叠中去除基底 具有各自具有阻挡金属膜的凸块的布线图案，以及从每个凸块去除阻挡金属膜。

公开(公告)号：US20040046582A1

公开(公告)日：2004-03-11

申请号：US10634925

申请日：2003-08-06

Applicant: HOYA CORPORATION

Inventor： Osamu Sugihara

IPC: G01R031/02

CPC classification number: G01R3/00 ,  G01R1/0735 ,  H05K1/09 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0323 ,  H05K2201/0367 ,  H05K2203/0733 ,  Y10T29/49204

Abstract: A contacting component has a probe contact formed by plating and adapted to be contacted with a target portion. The probe contact is made of a polycrystalline material having a crystal grain size not smaller than 10 nm and not greater than 40 nm

Abstract translation: 接触部件具有由电镀形成的适于与目标部分接触的探针接触。 探针接触由晶体尺寸不小于10nm且不大于40nm的多晶材料制成

公开(公告)号：US06700070B1

公开(公告)日：2004-03-02

申请号：US09705369

申请日：2000-11-03

Applicant: Stephen V. R. Hellriegel ,  Alexander I. Yatskov

Inventor： Stephen V. R. Hellriegel ,  Alexander I. Yatskov

IPC: H05K100

CPC classification number: H05K1/0266 ,  H05K1/0269 ,  H05K1/0393 ,  H05K3/0008 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/243 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/166 ,  H05K2203/167

Abstract: The field of the manufacture of electronic components, specifically to manufacturing flexible conductive strips having contact pads thereon, wherein a first set of alignment marks are provided on a substrate. Using the first set of alignment marks, several electronic components are formed in selected positions on the substrate. The electronic components may be formed in various groups, with a first group being formed using a first mask then, subsequent groups being formed using subsequent masks. Each of the respective masks are aligned with the first set of alignment marks in order to position the electronic components formed using the masks at the desired locations on the substrate. A second set of alignment marks are produced using the same mask as a set of electronic components that are located on the substrate. Subsequently, when a different set of features is produced, it is positioned using the second set of alignment marks located on the individual parts. Thus, tolerances can be achieved that would normally be possible only in the manufacture of individual parts, while still obtaining the advantages of the economies of scale possible by making many parts on a large sheet.

Abstract translation: 电子部件的制造领域，特别是制造其上具有接触焊盘的柔性导电条，其中第一组对准标记设置在基板上。 使用第一组对准标记，在基板上的选定位置形成几个电子部件。 电子部件可以形成为各种组，第一组使用第一掩模形成，然后使用后续掩模形成随后的组。 各个掩模中的每一个对准第一组对准标记，以便将使用掩模形成的电子部件定位在基板上的所需位置。第二组对准标记使用与一组电子装置相同的掩模 位于基板上的部件。 随后，当产生不同的特征集合时，使用位于各个部件上的第二组对准标记进行定位。 因此，可以实现通常仅在制造单个零件时可以实现的公差，同时通过在许多部件上制作大尺寸片而获得规模经济的优点。

公开(公告)号：US06686758B1

公开(公告)日：2004-02-03

申请号：US09534822

申请日：2000-03-23

Applicant: Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

Inventor： Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

IPC: G01R3102

CPC classification number: G01R1/07314 ,  H01L2924/00013 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10S438/978 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2224/29099

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract translation: 一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组， 半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。 公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

公开(公告)号：US06684497B2

公开(公告)日：2004-02-03

申请号：US09789156

申请日：2001-02-20

Applicant: Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

Inventor： Bernd Karl-Heinz Appelt ,  James Russell Bupp ,  Donald Seton Farquhar ,  Ross William Keesler ,  Michael Joseph Klodowski ,  Andrew Michael Seman ,  Gary Lee Schild

IPC: H01K310

CPC classification number: H05K3/4007 ,  H05K3/06 ,  H05K3/20 ,  H05K3/427 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/0733 ,  H05K2203/1572 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.

Abstract translation: 一种形成印刷电路板的方法，该印刷电路板包括具有基本上共面的上表面的多个导电凸块。 该方法包括以下步骤：将金属层施加到电介质基片上; 将第一光致抗蚀剂施加到所述基底上并暴露和显影所述第一光致抗蚀剂以限定导电凸块的图案; 蚀刻由所述显影暴露的金属层以形成所述多个导电凸块; 去除所述第一光致抗蚀剂; 在所述金属层上施加第二光致抗蚀剂; 曝光和显影所述第二光致抗蚀剂以限定导电凸块和电路线的图案; 蚀刻由所述显影曝光的金属层，以在所述金属层中形成电路线图案; 并除去所述第二光致抗蚀剂。 本发明还提供一种制备增强板的方法。

公开(公告)号：US06670698B1

公开(公告)日：2003-12-30

申请号：US10068717

申请日：2002-02-05

Applicant: Thomas P. Glenn ,  Steven Webster ,  Roy Dale Hollaway

Inventor： Thomas P. Glenn ,  Steven Webster ,  Roy Dale Hollaway

IPC: H01L23495

CPC classification number: H05K3/325 ,  H01L23/04 ,  H01L24/48 ,  H01L24/72 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10719 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.

Abstract translation: 封装的电子器件包括形成在衬底的第二表面上的接触焊盘上的连接触头。 与现有技术相比，连接触点不是焊接触点，而是由镀镍/镀铝的铜形成，因此比现有技术的焊球更硬，更不可塑并且变形。 连接触点被形成为与形成在母板或其他系统部件上的附接焊盘对准并接触。 然后使用张紧装置将本发明的包装电子装置机械地附接到母板。

公开(公告)号：US20030218190A1

公开(公告)日：2003-11-27

申请号：US10373670

申请日：2003-02-24

Applicant: SEIKO EPSON CORPORATION

Inventor： Nobuaki Hashimoto

IPC: H01L031/0328

CPC classification number: H05K3/361 ,  H01L2224/73204 ,  H05K1/117 ,  H05K3/28 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09709 ,  H05K2201/10977 ,  H05K2203/0369

Abstract: A plurality of lands are arranged in rows. The lands in adjacent rows are disposed in a staggered arrangement. A first interconnecting line is pulled out from each of the lands. Each of the lands is wider than the first interconnecting line in the row direction. A plurality of electrical connection sections are arranged in rows. The electrical connection sections in adjacent rows are disposed in a staggered arrangement. The lands are electrically connected with the electrical connection sections so as to overlap. Each of the electrical connection sections is a part of a second interconnecting line, and an insulating layer is formed between the second interconnecting lineing pattern other than the electrical connection sections and the first interconnecting lineing pattern.

Abstract translation: 多个平台排成行。 相邻行中的平台以交错排列布置。 从每个焊盘拉出第一互连线。 每个平台比行方向上的第一互连线宽。 多个电连接部分排列成行。 相邻行中的电连接部分以交错布置设置。 焊盘与电连接部分电连接以便重叠。 每个电连接部分是第二互连线的一部分，并且绝缘层形成在第二互连线图案之外，而不是电连接部分和第一互连线条图案。