公开(公告)号：US20240213088A1

公开(公告)日：2024-06-27

申请号：US18595951

申请日：2024-03-05

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Hao JIANG ,  Shi YOU ,  Mehul B. NAIK

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76879

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

公开(公告)号：US20220359224A1

公开(公告)日：2022-11-10

申请号：US17307383

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Hao JIANG ,  Chi LU ,  He REN ,  Mehul NAIK

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/67 ,  H01J37/32

Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

公开(公告)号：US20220285212A1

公开(公告)日：2022-09-08

申请号：US17193994

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Hao JIANG ,  Shi YOU ,  Mehul B. NAIK

IPC: H01L21/768

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

公开(公告)号：US20200027782A1

公开(公告)日：2020-01-23

申请号：US16037985

申请日：2018-07-17

Applicant: Applied Materials, Inc.

Inventor： Hao JIANG ,  He REN ,  Hao CHEN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

Abstract: Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.

公开(公告)号：US20180315650A1

公开(公告)日：2018-11-01

申请号：US15498024

申请日：2017-04-26

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.

公开(公告)号：US20150357183A1

公开(公告)日：2015-12-10

申请号：US14298102

申请日：2014-06-06

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK

IPC: H01L21/02 ,  H01L21/033 ,  H01L23/00

CPC classification number: H01L21/02063 ,  H01J37/321 ,  H01J37/32477 ,  H01J37/32642 ,  H01J37/32715 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76808 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.

Abstract translation: 用于形成双镶嵌结构的方法和装置，其利用选择性保护过程来保护双镶嵌结构中的通孔和/或沟槽，同时从双镶嵌结构去除硬掩模层。 在一个实施例中，用于从衬底去除图案化硬掩模层的方法包括在双镶嵌结构上形成有机聚合物材料，其暴露基本上设置在双镶嵌结构的上表面上的图案化硬掩模层， 并且从衬底去除有机聚合物材料。

公开(公告)号：US20240363354A1

公开(公告)日：2024-10-31

申请号：US18636449

申请日：2024-04-16

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Raman GAIRE ,  Shi YOU ,  Pranav RAMESH ,  Houssam LAZKANI ,  Shawn THOMAS ,  Abhishek DUBE ,  Mehul B. NAIK ,  Songkram Sonny SRIVATHANAKUL

IPC: H01L21/285 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/28518 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/401

Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

公开(公告)号：US20230187276A1

公开(公告)日：2023-06-15

申请号：US18108338

申请日：2023-02-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Jay Martin SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/76837 ,  H01L21/76828 ,  H01L21/76826 ,  H01L21/02337 ,  H01L21/76825 ,  H01L21/02323 ,  H01L21/76834 ,  H01L21/67103 ,  H01L21/02326

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20210233765A1

公开(公告)日：2021-07-29

申请号：US17153450

申请日：2021-01-20

Applicant: Applied Materials, Inc.

Inventor： Naomi YOSHIDA ,  He REN ,  Hao JIANG ,  Chenfei SHEN ,  Chi-Chou LIN ,  Hao CHEN ,  Xuesong LU ,  Mehul B. NAIK

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/66 ,  B08B5/02

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

公开(公告)号：US20180366328A1

公开(公告)日：2018-12-20

申请号：US15988854

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Minrui YU ,  Mehul B. NAIK

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/67

CPC classification number: H01L21/2855 ,  C23C14/0682 ,  C23C14/3464 ,  C23C14/352 ,  H01J37/3417 ,  H01J37/3429 ,  H01J37/3435 ,  H01J37/3447 ,  H01L21/32053 ,  H01L21/67138 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53271

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.