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    Method of forming a semiconductor socket
    23.
    发明授权
    Method of forming a semiconductor socket 有权
    形成半导体插座的方法

    公开(公告)号：US09320144B2

    公开(公告)日：2016-04-19

    申请号：US13319158

    申请日：2010-06-15

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H05K3/00 ,  H05K1/14 ,  H01R12/57 ,  H05K3/34 ,  H01R12/52

    CPC classification number: H05K1/141 ,  H01R12/52 ,  H01R12/57 ,  H05K3/3436 ,  H05K2201/0311 ,  H05K2201/049 ,  H05K2201/10295 ,  H05K2201/10719 ,  Y10T29/49139 ,  Y10T29/49147

    Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

    Abstract translation: 一种半导体插座，包括具有从第一表面延伸到第二表面的多个通孔的基板。 多个离散接触构件位于多个通孔中。 多个接触构件各自包括可从第二表面接近的近端和在第一表面上方延伸的远端。 至少一个电介质层与基板的第二表面结合，其凹部对应于目标电路几何形状。 沉积在至少一部分凹陷中的导电材料以形成重新分布接触构件的近端的端子间距的导电迹线。

    Electrical interconnect IC device socket
    24.
    发明授权
    Electrical interconnect IC device socket 有权
    电气互连IC器件插座

    公开(公告)号：US09276339B2

    公开(公告)日：2016-03-01

    申请号：US13880231

    申请日：2011-11-29

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H01R12/70 ,  H01R11/16 ,  H01R12/71 ,  H05K7/10 ,  H01R43/00 ,  H01R13/24

    CPC classification number: H01R12/7082 ,  H01R11/16 ,  H01R12/714 ,  H01R13/24 ,  H01R43/00 ,  H05K7/1061 ,  Y10T29/49208

    Abstract: A surface mount electrical interconnect adapted to provide an interface between contact pads on an LGA device and a PCB. The electrical interconnect includes a socket substrate having a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. A plurality of contact members are located in the socket substrate such that first contact tips are located proximate the first openings, second contact tips are located proximate the second openings, and center portions located in the center openings.

    Abstract translation: 适于在LGA器件和PCB之间提供接触焊盘之间的接口的表面贴装电互连。 电互连包括具有第一表面的插座衬底，第一表面具有多个具有第一横截面的第一开口，具有多个具有第二横截面的第二开口的第二表面和连接第一和第二开口的中心开口。 中心开口包括大于第一和第二横截面的至少一个横截面。 多个接触构件位于插座衬底中，使得第一接触尖端位于第一开口附近，第二接触尖端位于第二开口附近，中心部分位于中心开口中。

    Metalized pad to electrical contact interface
    25.
    发明授权
    Metalized pad to electrical contact interface 有权
    金属化垫到电气接触界面

    公开(公告)号：US09276336B2

    公开(公告)日：2016-03-01

    申请号：US13410914

    申请日：2012-03-02

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H01R12/00 ,  H01R12/57 ,  H01R12/52 ,  H01R12/71 ,  H05K7/10 ,  H05K1/14 ,  H05K3/34 ,  H05K3/40

    CPC classification number: H01R12/57 ,  H01R12/52 ,  H01R12/523 ,  H01R12/716 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4046 ,  H05K7/1069 ,  H05K2201/049 ,  Y10T29/49124

    Abstract: A surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device. The electrical interconnect includes a substrate with a plurality of recesses arranged along a first surface to correspond to the contacts on the integrated circuit device. Contact members are located in a plurality of the recess. The contact members include contact tips adapted to electrically couple with the contacts on the integrated circuit device. An electrical interface including at least one circuit trace electrically couples the contact member to metalized pads located along a second surface of the substrate at a location offset from a corresponding contact member. A solder ball is attached to a plurality of the metalized pads.

    Abstract translation: 表面安装电互连，以提供PCB与集成电路器件上的触点之间的接口。 电互连包括具有沿着第一表面布置以对应于集成电路器件上的触点的多个凹槽的衬底。 接触构件位于多个凹部中。 接触构件包括适于与集成电路器件上的触点电耦合的接触尖端。 包括至少一个电路迹线的电接口将电接触构件电耦合到沿着衬底的第二表面位于偏离对应接触构件的位置的金属化焊盘。 焊球连接到多个金属化焊盘。

    Compliant core peripheral lead semiconductor test socket
    26.
    发明授权
    Compliant core peripheral lead semiconductor test socket 有权
    兼容核心外围引线半导体测试插座

    公开(公告)号：US08610265B2

    公开(公告)日：2013-12-17

    申请号：US13448865

    申请日：2012-04-17

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: H01L23/34

    CPC classification number: H01L23/34 ,  G01R1/0416 ,  H01L23/522 ,  H01L2224/13 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/10378 ,  H05K2203/162 ,  Y10T29/49165

    Abstract: An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate.

    Abstract translation: 用于在IC器件上的端子和印刷电路板（PCB）上的接触焊盘之间提供临时互连的电互连。 电互连包括具有第一表面的基板，该第一表面具有多个开口，其布置成对应于IC器件上的端子。 柔性材料位于开口中。 多个导电迹线沿着衬底的第一表面延伸到柔性材料上。 柔性材料提供抵抗导电迹线弯曲到开口中的偏置力。 导电结构电连接到开口上的导电迹线。 导电结构适于增强与IC器件上的端子的电耦合。 电气延伸通过衬底的通孔将导电迹线耦合到位于衬底的第二表面附近的PCB端子。

    COMPLIANT WAFER LEVEL PROBE ASSEMBLY
    28.
    发明申请
    COMPLIANT WAFER LEVEL PROBE ASSEMBLY 有权
    合适的水平探头组件

    公开(公告)号：US20120068727A1

    公开(公告)日：2012-03-22

    申请号：US13266522

    申请日：2010-05-25

    Applicant: James Rathburn

    Inventor： James Rathburn

    IPC: G01R1/067 ,  G01R31/28 ,  H01R43/00

    CPC classification number: G01R1/07314

    Abstract: A probe assembly that acts as a temporary interconnect between terminals on a circuit member and a test station. The probe assembly can include a base layer of a dielectric material printed onto a surface of a fixture. The surface of the fixture can have a plurality of cavities. A plurality of discrete contact members can be formed in the plurality of cavities in the fixture and coupled to the base layer. A plurality of conductive traces can be printed onto an exposed surface of the base layer and electrically coupled with proximal ends of one or more of the discrete contact members. A compliant layer can be deposited over the conductive traces and the proximal ends of the contact members. A protective layer can be deposited on the compliant layer such that when the probe assembly is removed from the fixture the distal ends of the contact members contact terminals on the circuit member and the conductive traces electrically couple the circuit member to a test station. Electrical devices on the probe assembly can communicate with the test station to provide adaptive testing.

    Abstract translation: 探针组件，用作电路元件端子和测试台之间的临时互连。 探针组件可以包括印刷在固定装置的表面上的电介质材料的基层。 固定装置的表面可以具有多个空腔。 多个离散的接触构件可以形成在固定装置中的多个空腔中并且耦合到基层。 多个导电迹线可以印刷到基底层的暴露表面上并与一个或多个离散接触构件的近端电耦合。 柔性层可以沉积在导电迹线和接触构件的近端上。 保护层可以沉积在柔性层上，使得当探针组件从固定装置移除时，接触构件的远端接触电路构件上的端子，并且导电迹线将电路构件电耦合到测试台。 探头组件上的电气设备可以与测试台通信以提供自适应测试。

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