公开(公告)号：US08563420B2

公开(公告)日：2013-10-22

申请号：US13561247

申请日：2012-07-30

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。

公开(公告)号：US20130241871A1

公开(公告)日：2013-09-19

申请号：US13803888

申请日：2013-03-14

Applicant: HANNSTAR DISPLAY CORP.

Inventor： CHENG-CHUNG HUANG ,  JENG-MAW CHIOU

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F2203/04103 ,  H05K3/027 ,  H05K2201/0175 ,  H05K2201/0326

Abstract: There is provided a touch panel including a substrate, at least one laser blocking layer and at least one transparent conductive layer. The at least one laser blocking layer is formed on at least one of a first surface and a second surface of the substrate. The at least one transparent conductive layer is formed on at least one of the first surface and the second surface of the substrate, and a plurality of etching trenches having irregular edges are formed on the transparent conductive layer using UV laser.

Abstract translation: 提供了一种包括基板，至少一个激光阻挡层和至少一个透明导电层的触摸面板。 所述至少一个激光阻挡层形成在所述基板的第一表面和第二表面中的至少一个上。 所述至少一个透明导电层形成在所述基板的所述第一表面和所述第二表面中的至少一个上，并且使用UV激光在所述透明导电层上形成具有不规则边缘的多个蚀刻沟槽。

公开(公告)号：US08468693B2

公开(公告)日：2013-06-25

申请号：US12868425

申请日：2010-08-25

Applicant: Tomohiko Katoh ,  Kenji Horino ,  Yuko Saya

Inventor： Tomohiko Katoh ,  Kenji Horino ,  Yuko Saya

IPC: H01R43/02

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01L27/016 ,  H05K1/162 ,  H05K3/38 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/2063 ,  H05K2203/1105 ,  Y10T29/49126 ,  Y10T29/49163 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: A dielectric device has a first conductor and a dielectric disposed thereon. An intermediate region is formed between the first conductor and dielectric. In the intermediate region, an additive different from the first conductor and dielectric and the dielectric are mixed with each other. The additive contains at least one element of Si, Al, P, Mg, Mn, Y, V, Mo, Co, Nb, Fe, and Cr.

Abstract translation: 电介质器件具有设置在其上的第一导体和电介质。 在第一导体和电介质之间形成中间区域。 在中间区域中，与第一导体和电介质和电介质不同的添加剂彼此混合。 添加剂含有Si，Al，P，Mg，Mn，Y，V，Mo，Co，Nb，Fe和Cr中的至少一种元素。

公开(公告)号：US08391015B2

公开(公告)日：2013-03-05

申请号：US12357867

申请日：2009-01-22

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/305 ,  H05K2201/0175 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10977

Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer being interposed between a first and a second electrode, and a semiconductor device mounting pad, including a first and a second pad, formed on an outermost resin insulating layer of the resin insulating layers. An underfill which covers an area larger than that of the high dielectric layer is formed, when the underfill covered area is projected along a lamination direction of the resin insulating layers to a face on which the high dielectric layer is formed. The capacitor is located immediately beneath the underfill covered area.

Abstract translation: 一种印刷线路板包括绝缘层和一个电容器，该电容器包括介于第一和第二电极之间的陶瓷高介电层，以及半导体器件安装衬垫，包括第一和第二衬垫，该衬底形成在第一和第二衬底的最外层树脂绝缘层上 树脂绝缘层。 当底层覆盖区域沿着树脂绝缘层的层叠方向突出到形成有高介电层的面时，形成覆盖比高介电层的面积大的面积的底部填充物。 电容器位于底部填充区域的正下方。

公开(公告)号：US08288875B2

公开(公告)日：2012-10-16

申请号：US12749117

申请日：2010-03-29

Applicant: Noriyoshi Shimizu ,  Akio Rokugawa

Inventor： Noriyoshi Shimizu ,  Akio Rokugawa

IPC: H01L23/48 ,  H01L21/04

CPC classification number: H05K3/28 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H05K3/3452 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/099 ,  H05K2203/0577 ,  H01L2224/0401

Abstract: A board on which a wiring having an electrode pad is formed is prepared. A resist film is formed on the board in order to cover the wiring and then the resist film is left on the electrode pad through patterning. An inorganic insulating film is formed on the board in order to cover the wiring and then the resist film is removed, thereby removing the inorganic insulating film provided on the resist film to leave the inorganic insulating film between the wirings. A solder resist layer is formed on the board in order to cover the wiring and then the electrode pad is exposed.

Abstract translation: 制备其上形成有电极焊盘的布线的板。 在板上形成抗蚀剂膜以覆盖布线，然后通过图案化将抗蚀剂膜留在电极焊盘上。 在板上形成无机绝缘膜以覆盖布线，然后除去抗蚀剂膜，从而除去设置在抗蚀剂膜上的无机绝缘膜，以使布线之间的无机绝缘膜离开。 在板上形成阻焊层以覆盖布线，然后暴露电极焊盘。

公开(公告)号：US20120234585A1

公开(公告)日：2012-09-20

申请号：US13395659

申请日：2010-09-09

Applicant: Wolfgang Schmidt ,  Kirsten Barth-Gremmel

Inventor： Wolfgang Schmidt ,  Kirsten Barth-Gremmel

IPC: H05K1/09 ,  H05K3/00 ,  B32B5/18

CPC classification number: B41M5/5218 ,  B41M5/506 ,  B41M5/52 ,  B41M5/5254 ,  H01L51/0096 ,  H05K1/0386 ,  H05K1/0393 ,  H05K3/1208 ,  H05K3/125 ,  H05K2201/0116 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0284 ,  H05K2201/05 ,  H05K2203/013 ,  Y02E10/549 ,  Y10S428/901 ,  Y10T428/24802 ,  Y10T428/249979

Abstract: Support materials for printing electrically conductive structures by means of inkjet printing with inks which contain conductive particles lead to low resistances for the printed structures without thermal post-treatment when they contain a microporous layer with a mean pore size of less than 100 nm as an outer layer.

Abstract translation: 用于通过喷墨印刷印刷导电结构的支撑材料，其中含有导电颗粒的油墨导致印刷结构的低电阻，当它们含有平均孔径小于100nm的微孔层作为外部时，无需热后处理 层。

公开(公告)号：US08254082B2

公开(公告)日：2012-08-28

申请号：US12374698

申请日：2008-01-25

Applicant: Akihiko Shirakawa ,  Ryuichi Mitsumoto ,  Koji Tokita

Inventor： Akihiko Shirakawa ,  Ryuichi Mitsumoto ,  Koji Tokita

IPC: H01G4/008

CPC classification number: H01G4/33 ,  H01G4/1218 ,  H01G4/20 ,  H01G9/0032 ,  H01G9/052 ,  H01G9/07 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/0315 ,  Y10T156/10 ,  Y10T428/266

Abstract: The capacitor material of the present invention is comprised by laminating a titanium dioxide layer and a titanate compound layer having perovskite crystals.

Abstract translation: 本发明的电容器材料通过层叠二氧化钛层和具有钙钛矿结晶的钛酸盐化合物层构成。

公开(公告)号：US20120189826A1

公开(公告)日：2012-07-26

申请号：US13498764

申请日：2010-09-28

Applicant: Katsura Hayashi

Inventor： Katsura Hayashi

IPC: B32B3/00 ,  B32B9/04 ,  B32B18/00 ,  B32B7/02

CPC classification number: H05K3/4673 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/1152 ,  Y10T428/24802 ,  Y10T428/24942

Abstract: A structure for which the electrical reliability is improved is provided. A structure in accordance with one embodiment includes an inorganic insulating layer including amorphous silicon oxide and having an elastic modulus which is 45 GPa or less. A method for manufacturing a structure in accordance with one embodiment includes applying an inorganic insulating sol including inorganic insulating particles composed of amorphous silicon oxide, and forming an inorganic insulating layer including amorphous silicon oxide and having an elastic modulus which is 45 GPa or less by heating the inorganic insulating particles at a temperature lower than a crystallization onset temperature of silicon oxide to each other.

Abstract translation: 提供了改善电可靠性的结构。 根据一个实施方案的结构包括无定形氧化硅的无机绝缘层，其弹性模量为45GPa以下。 根据一个实施方案的结构的制造方法包括：施加包含由无定形氧化硅构成的无机绝缘粒子的无机绝缘溶胶，通过加热形成包含非晶氧化硅的无机绝缘层，其弹性模量为45GPa以下 所述无机绝缘粒子的温度低于氧化硅的结晶化开始温度。

公开(公告)号：US20120155038A1

公开(公告)日：2012-06-21

申请号：US13392247

申请日：2010-07-28

Applicant: Yasumori Fukushima ,  Masaki Fujiwara ,  Steven Roy Droes

Inventor： Yasumori Fukushima ,  Masaki Fujiwara ,  Steven Roy Droes

IPC: H05K1/02 ,  H05K3/20 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K1/185 ,  H01L21/4846 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/189 ,  H05K3/08 ,  H05K2201/0175 ,  H05K2203/016 ,  H05K2203/0384 ,  H05K2203/095 ,  H05K2203/1469 ,  Y10T29/49128 ,  H01L2924/00

Abstract: The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board (20), a second insulating layer (24) made of an inorganic material is positioned between a wiring layer (25) and a first insulating layer (23) made of an inorganic material.

Abstract translation: 本发明提供一种具有优异的柔性，精细布线图案和精细电触点的高性能柔性电路板及其制造方法。 在柔性电路板（20）中，由无机材料制成的第二绝缘层（24）位于布线层（25）和由无机材料制成的第一绝缘层（23）之间。

公开(公告)号：US20120152601A1

公开(公告)日：2012-06-21

申请号：US13374858

申请日：2012-01-19

Applicant: Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05K1/03 ,  B23K1/20 ,  B23K31/02 ,  B05D5/12 ,  B05D3/00

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Abstract translation: 描述了用于封装衬底和管芯间隔件的层或层。 层或层包括位于平面内并由金属通孔分开的多个陶瓷阱。 陶瓷井内的凹陷由介电填料材料占据。