公开(公告)号：US20140003004A1

公开(公告)日：2014-01-02

申请号：US13922622

申请日：2013-06-20

Applicant: Seiko Epson Corporation

Inventor： Tomoyuki KAMAKURA

IPC: H05K7/00 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K7/00 ,  H01L2224/16225 ,  H03H9/0509 ,  H03H9/1021 ,  H05K1/0306 ,  H05K1/18 ,  H05K3/246 ,  H05K3/30 ,  H05K3/321 ,  H05K2201/0347 ,  H05K2201/10083 ,  H05K2201/10371 ,  H05K2203/1131 ,  H05K2203/1147 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: A method for producing a base substrate includes preparing an insulator substrate; forming a first film containing, as a main component, a metal that contains at least one of tungsten and molybdenum and has a melting point of 1000° C. or higher on the insulator substrate; forming a second film containing nickel as a main component and also containing boron on the first film; forming a first metal layer by performing a sintering treatment of the first film and the second film; and forming a second metal layer containing palladium as a main component on the first metal layer.

Abstract translation: 一种制造基底基板的方法包括：制备绝缘体基板; 在所述绝缘体基板上形成含有含有钨和钼中的至少一种且熔点为1000℃以上的金属作为主要成分的第一膜， 在第一膜上形成含有镍作为主要成分并且还含有硼的第二膜; 通过对所述第一膜和所述第二膜进行烧结处理来形成第一金属层; 以及在所述第一金属层上形成含有钯作为主要成分的第二金属层。

公开(公告)号：US08604606B2

公开(公告)日：2013-12-10

申请号：US12845299

申请日：2010-07-28

Applicant: Joo-yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

Inventor： Joo-yang Eom ,  O-seob Jeon ,  Seung-won Lim ,  Seung-yong Choi

IPC: H01L23/10 ,  H01L23/34

CPC classification number: H01L23/3675 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/562 ,  H01L25/165 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/0061 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3484 ,  H05K2201/0347 ,  H05K2201/09745 ,  H05K2203/0315 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

Abstract translation: 提供一种其中半导体封装和散热器彼此结合的散热器封装及其制造方法。 散热器封装包括在其上表面上具有空腔的散热器; 形成在空腔的底面上的金属层; 形成在所述金属层上的焊膏层; 焊膏层上的基板; 以及安装在基板上的引线和半导体芯片。

公开(公告)号：US08575492B2

公开(公告)日：2013-11-05

申请号：US13396485

申请日：2012-02-14

Applicant: Lee H. Tullidge ,  Leonard De Oto ,  Tim Larson ,  Patrick O'Keefe ,  Herb Gertz

Inventor： Lee H. Tullidge ,  Leonard De Oto ,  Tim Larson ,  Patrick O'Keefe ,  Herb Gertz

IPC: H05K1/00

CPC classification number: H05K1/0206 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/1492 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A device and method of heat sinking a surface mount device (SMD) component. In an example method through holes are formed in a printed circuit board (PCB), a first copper layer is electroless plated in the holes, a second copper layer is standard plated in the holes and surrounding surfaces of the PCB, a third copper layer is masked and pulse plated in the holes, the holes are filled with non-conductive material and then is sanded flush with the second copper layer. A fourth copper layer electroless plated on the PCB over the area of the holes, a fifth copper layer (or pad) plated on the PCB over the area of the holes, and a surface mount device is attached to the fifth copper layer.

Abstract translation: 散热表面贴装器件（SMD）元件的器件和方法。 在一个示例性方法中，通孔形成在印刷电路板（PCB）中，第一铜层被无电镀在孔中，第二铜层标准镀在PCB的孔和周围表面中，第三铜层是 屏蔽并脉冲电镀在孔中，孔中填充有非导电材料，然后与第二铜层进行砂光冲洗。 在PCB上的无孔电镀第四铜层，在孔的区域上镀有PCB上的第五铜层（或焊盘），以及表面贴装装置附着在第五铜层上。

公开(公告)号：US20130206467A1

公开(公告)日：2013-08-15

申请号：US13846875

申请日：2013-03-18

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K3/06 ,  H05K1/02

CPC classification number: H05K3/06 ,  H05K1/0298 ,  H05K3/465 ,  H05K2201/0347 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A circuit board includes a circuit substrate, a first dielectric layer, a first conductive layer, a second conductive layer and a second dielectric layer. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer, and an intaglio pattern. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via. The second conductive layer is electrically connected to the first circuit layer via the first conductive layer. The second dielectric layer is disposed on the first dielectric layer and covers the second conductive layer and the second surface of the first dielectric layer.

Abstract translation: 电路板包括电路基板，第一介电层，第一导电层，第二导电层和第二介电层。 电路基板具有第一表面和第一电路层。 第一电介质层设置在电路基板上并覆盖第一表面和第一电路层。 第一电介质层具有第二表面，至少从第二表面延伸到第一电路层的盲孔以及凹版图案。 第一导电层设置在盲孔中。 第二导电层设置在凹版图案和盲孔中。 第二导电层经由第一导电层电连接到第一电路层。 第二电介质层设置在第一电介质层上并覆盖第二导电层和第一介电层的第二表面。

公开(公告)号：US08484832B2

公开(公告)日：2013-07-16

申请号：US12791701

申请日：2010-06-01

Applicant: Garo Miyamoto

Inventor： Garo Miyamoto

IPC: H01C17/00

CPC classification number: H05K1/167 ,  H05K3/243 ,  H05K3/4069 ,  H05K2201/0323 ,  H05K2201/0347 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2203/107 ,  H05K2203/171 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: There is provided a method of producing a printed circuit board incorporating a resistance element capable of adjusting resistance after the resistance element has been formed and assuring a high accurate resistance. A method of producing a printed circuit board incorporating a resistance element using carbon paste includes the steps of: forming through holes 5, 6, 25 and 26 or a bottomed hole in a double-sided copper clad laminate; applying noble metal plating into the through hole or the bottomed hole; filling the through hole or the bottomed hole with carbon paste; subjecting the carbon paste with which the thorough hole or the bottomed hole is filled to noble metal plating, conducting treatment and plating to form a conductive layer; forming an opening 18 in the conductive layer on the end of the through hole filled with the carbon paste; and performing trimming through the opening to adjust the resistance of the resistor formed by the carbon paste.

Abstract translation: 提供了一种制造印刷电路板的方法，该印刷电路板包括能够在电阻元件形成之后能够调节电阻的电阻元件并且确保高精度的电阻。 制造使用碳膏包含电阻元件的印刷电路板的方法包括以下步骤：在双面铜箔层压板中形成通孔5,62,26或有底孔; 将贵金属电镀施加到通孔或有底孔中; 用碳浆填充通孔或有孔孔; 对填充有通孔或有底孔的碳糊进行贵金属电镀，进行处理和电镀以形成导电层; 在填充有碳糊的通孔的端部的导电层中形成开口18; 并通过开口进行修整以调节由碳浆形成的电阻器的电阻。

公开(公告)号：US08395866B1

公开(公告)日：2013-03-12

申请号：US12540870

申请日：2009-08-13

Applicant: Christopher Schreiber ,  Christopher Dunn

Inventor： Christopher Schreiber ,  Christopher Dunn

IPC: G11B5/48

CPC classification number: G11B5/48 ,  B33Y80/00 ,  G11B5/486 ,  H05K1/056 ,  H05K3/388 ,  H05K3/44 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K2201/09827

Abstract: A disk drive suspension circuit has copper signal conductors connected by vias through an insulative layer to respective stainless steel flying leads. The stainless steel flying leads are activated and plated with one or more metals, with a final layer over the flying lead being a layer such as gold, suitable for bonding to form bond pads. The gold bond pads may be attached using thermosonic welding, solder ball bonding, or other suitable methods to an electrical component such as wires or a the disk drive's pre-amp circuit.

Abstract translation: 磁盘驱动器悬挂电路具有通过绝缘体通过绝缘体连接到相应的不锈钢飞行导线的铜信号导体。 不锈钢飞行引线被激活并且镀有一种或多种金属，飞溅引线上的最终层是诸如金的层，适于粘合以形成接合焊盘。 金焊盘可以使用热超声波焊接，焊球接合或其它合适的方法附接到电气部件，例如电线或磁盘驱动器的前置放大器电路。

公开(公告)号：US08378227B2

公开(公告)日：2013-02-19

申请号：US12585754

申请日：2009-09-24

Applicant: Seiichi Inoue

Inventor： Seiichi Inoue

IPC: H05K1/11

CPC classification number: H05K3/246 ,  H05K1/0256 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/1208 ,  H05K3/125 ,  H05K3/28 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2201/09036 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/1147 ,  H05K2203/1173 ,  Y10T29/49155

Abstract: A method of forming a wiring board comprises: a step of forming a receptive layer having a porous structure on a substrate; a step of forming wiring portions in a desired conductive pattern on a surface of the receptive layer by ejecting a colloidal metal solution for drawing by an ink-jet system based on image date of the conductive pattern; and a step of performing a migration-proof treatment on at least part of the receptive layer exposed between mutually adjacent wiring portions.

Abstract translation: 形成布线板的方法包括：在基板上形成具有多孔结构的接收层的步骤; 基于导电图案的图像日期，通过喷射通过喷墨系统进行拉伸的胶体金属溶液，在接收层的表面上形成所需导电图案中的布线部分的步骤; 以及对相互相邻的布线部之间露出的接受层的至少一部分进行防迁移处理的步骤。

公开(公告)号：US08309969B2

公开(公告)日：2012-11-13

申请号：US12623135

申请日：2009-11-20

Applicant: Yoshinobu Suehiro ,  Koji Tasumi

Inventor： Yoshinobu Suehiro ,  Koji Tasumi

IPC: H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00

CPC classification number: H05K1/021 ,  F21K9/00 ,  F21K9/232 ,  F21K9/90 ,  F21V5/043 ,  F21V7/005 ,  F21V29/505 ,  F21V29/70 ,  F21V29/75 ,  F21V29/763 ,  F21V29/767 ,  F21Y2103/10 ,  F21Y2115/10 ,  G02B6/0068 ,  G02B6/0085 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2924/01019 ,  H01L2924/09701 ,  H05K3/341 ,  H05K2201/0347 ,  H05K2201/0373 ,  H05K2201/10106 ,  H05K2201/10969 ,  H01L2924/00014

Abstract: A light emitting device includes a light-emitting portion including a metal part including a metal able to be bonded to a solder material, and a heat dissipation member that includes aluminum, aluminum alloy, magnesium or magnesium alloy and a bonding portion processed to be bonded to the solder material. The metal part of the light-emitting portion is bonded via the solder material to the bonding portion of the heat dissipation member. The solder material includes a material unable to be directly bonded to the heat dissipation member, the metal part of the light-emitting portion is formed by metalizing an insulation of ceramic or semiconductor, and the bonding portion includes a thermal expansion coefficient between that of the heat dissipation member and that of the insulation.

Abstract translation: 发光装置包括：发光部，其包括具有能够与焊料接合的金属的金属部，以及包含铝，铝合金，镁或镁合金的散热构件和加工成粘合的接合部 焊接材料。 发光部的金属部通过焊料粘合到散热部件的接合部。 焊料材料包括不能直接接合到散热构件的材料，发光部分的金属部分通过金属化陶瓷或半导体的绝缘体而形成，并且接合部分包括热膨胀系数 散热构件和隔热构件。

公开(公告)号：US08294034B2

公开(公告)日：2012-10-23

申请号：US12789895

申请日：2010-05-28

Applicant: Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen

IPC: H05K1/00 ,  H05K1/11

CPC classification number: H05K3/465 ,  H05K3/184 ,  H05K2201/0347 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract translation: 提供了包括电路基板，第一介电层，拮抗激活层，第一导电层，第二导电层和第二介电层的电路板。 电路基板具有第一表面和第一电路层。 第一电介质层设置在电路基板上并覆盖第一表面和第一电路层。 第一介电层具有第二表面，至少一个从第二表面延伸到第一电路层的盲孔和凹版图案。 拮抗活化层设置在电介质层的第二表面上。 第一导电层设置在盲孔中。 第二导电层设置在凹版图案和盲孔中并覆盖第一导电层。 第二导电层经由第一导电层与第一电路层电连接。

公开(公告)号：US08227702B2

公开(公告)日：2012-07-24

申请号：US12385134

申请日：2009-03-31

Applicant: Hatsuo Ikeda ,  Koji Ichikawa

Inventor： Hatsuo Ikeda ,  Koji Ichikawa

IPC: H05K1/09

CPC classification number: H05K1/113 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K3/246 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2201/09745 ,  H01L2224/05599

Abstract: A multilayer ceramic substrate in which an active element and a passive element are surface-equipped over the outermost surface on one side is provided. The multilayer ceramic substrate comprises a plurality of laminated ceramic substrate layers, a surface layer terminal electrode provided in a via hole of an outermost ceramic substrate layer on at least one side and having a surface layer via electrode and a metal plating layer deposited over an end surface of the surface layer via electrode, and a via conductor which connects the surface layer terminal electrode and circuit patterns over the ceramic substrate layer at the inside, wherein a via hole size of a surface layer terminal electrode for connection of the active element is smaller than a via hole size of a surface layer terminal electrode for connection of the passive element.

Abstract translation: 提供一种多层陶瓷基板，其中在一侧的最外表面上表面配置有源元件和无源元件。 多层陶瓷基板包括多个层叠陶瓷基板层，表面层端子电极，设置在至少一侧的最外侧陶瓷基板层的通路孔中，具有表面层通孔电极和沉积在端部的金属镀层 表面层通孔电极的表面，以及将内表面层端子电极和电路图案连接在陶瓷基板层上的通孔导体，其中用于连接有源元件的表面层端子电极的通孔尺寸较小 比用于连接无源元件的表面层端子电极的通孔尺寸。