公开(公告)号：US11963302B2

公开(公告)日：2024-04-16

申请号：US17412314

申请日：2021-08-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masato Nomiya

IPC: H05K1/11 ,  H05K1/09

CPC classification number: H05K1/117 ,  H05K1/09 ,  H05K2201/0364 ,  H05K2201/0919

Abstract: An electronic component includes a substrate and side wires. The substrate includes a first major surface, a second major surface, and a side surface. The side wires are on the side surface of the substrate and spaced apart from each other in a direction along an outer periphery of the substrate when viewed in plan in a thickness direction of the substrate. At least a portion of each of the side wires is provided indirectly on the side surface of the substrate. The electronic component further includes an electrically insulating layer interposed between the side surface of the substrate and the at least a portion of each of the side wires. Each of the side wires includes a bent portion bent when viewed in plan in the thickness direction of the substrate.

公开(公告)号：US11723143B1

公开(公告)日：2023-08-08

申请号：US17730856

申请日：2022-04-27

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Chang Kyu Choi ,  Hyun Mo Ku ,  Sarah Kay Haney ,  Li Sun

IPC: H05K1/02

CPC classification number: H05K1/0209 ,  H05K2201/0364 ,  H05K2201/062 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/10098 ,  H05K2201/10318

Abstract: A system and method for dissipating heat from a package and reducing interference between signaling pins is disclosed. The system includes a circuit substrate that includes a dielectric layer and at least one metal layer having an external surface. A plurality of metal posts is disposed on the external surface that function to a least one of dissipate heat from the circuit substrate, shield interfering signals between the signaling pins, and interact with mounting substrates on corresponding componentry. One or more metal posts are merged, increasing the interference shielding and heat dissipation functions of the metal posts.

公开(公告)号：US09656912B2

公开(公告)日：2017-05-23

申请号：US14967348

申请日：2015-12-13

Applicant: Tsinghua University ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： Yuan-Hao Jin ,  Qun-Qing Li ,  Shou-Shan Fan

IPC: H05K1/00 ,  C03C17/09 ,  C23C14/20 ,  C23C14/58 ,  C23C16/06 ,  C23C16/56 ,  C23C30/00 ,  C23F4/00 ,  G06F3/044 ,  G06F3/047 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09

CPC classification number: B32B15/08 ,  B32B5/028 ,  B32B2307/202 ,  C03C17/09 ,  C03C2217/252 ,  C03C2217/253 ,  C03C2217/255 ,  C03C2218/15 ,  C03C2218/33 ,  C03C2218/34 ,  C23C14/20 ,  C23C14/5826 ,  C23C14/5873 ,  C23C16/06 ,  C23C16/56 ,  C23C30/00 ,  C23F4/00 ,  G06F3/044 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04112 ,  H01B1/026 ,  H01B1/16 ,  H05K1/0274 ,  H05K1/028 ,  H05K1/03 ,  H05K1/09 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0364 ,  H05K2201/09681

Abstract: The disclosure relates to a metal nanowire film. The metal nanowire film includes a substrate and a number of first metal nanowire bundles located on the substrate. The number of first metal nanowire bundles are parallel with and spaced from each other. Each of the number of first metal nanowire bundles includes a number of first metal nanowires parallel with each other. The first distance between adjacent two of the number of first metal nanowires is less than the second distance between adjacent two of the number of first metal nanowire bundles.

公开(公告)号：US20170027056A1

公开(公告)日：2017-01-26

申请号：US14919442

申请日：2015-10-21

Applicant: Okins Electronics Co., Ltd.

Inventor： Jin Kook Jun ,  Sung Gye Park ,  Jae Weon Shim ,  Sang Hoon Cha

IPC: H05K1/11 ,  H05K1/02 ,  G01R1/04

CPC classification number: H05K1/11 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/07342 ,  G01R1/0735 ,  H05K1/028 ,  H05K2201/0364

Abstract: A microelectromechanical system (MEMS) film for a test socket is arranged between a semiconductor device and a test apparatus for performing an electrical test of the semiconductor device and includes a flexible bare film and a plurality of round-type MEMS bumps on the bare film, each of the MEMS bumps being formed on the bare film by using a MEMS processing technique, having an electrical contact with an electrode pad of the test apparatus or a conductive ball of the semiconductor device, and having a contact surface rounded from an edge side toward a center side in a convex manner in a direction toward the electrode pad or the conductive ball.

Abstract translation: 用于测试插座的微电子机械系统（MEMS）膜布置在半导体器件和用于执行半导体器件的电测试的测试装置之间，并且在裸膜上包括柔性裸片和多个圆形MEMS凸块， 每个MEMS凸块通过使用MEMS处理技术形成在裸膜上，该MEMS处理技术与测试装置的电极焊盘或半导体器件的导电球电接触，并且具有从边缘侧朝向 在朝向电极焊盘或导电球的方向上呈凸形的中心侧。

公开(公告)号：US20160037629A1

公开(公告)日：2016-02-04

申请号：US14813218

申请日：2015-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Nobuya TAKAHASHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K3/18 ,  H01L21/4857 ,  H01L23/49866 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0296 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/111 ,  H05K1/141 ,  H05K3/16 ,  H05K3/4007 ,  H05K2201/0326 ,  H05K2201/0364 ,  H05K2201/0391 ,  H05K2201/0769 ,  H05K2201/09236 ,  H05K2201/0929 ,  H05K2201/094 ,  H05K2201/09654 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/014

Abstract: A printed wiring board includes an insulation layer, conductive pads formed on the insulation layer and positioned to connect an electronic component, and a conductive wiring pattern including first and second conductive patterns and formed on the insulation layer such that the conductive wiring pattern is extending between the conductive pads. The first pattern includes first wiring lines, the second pattern includes second wiring lines, the first and second conductive patterns are formed such that the first wiring lines and the second wiring lines are alternately arrayed on the insulation layer, each of the first wiring lines includes a first metal layer formed on an interface with the insulation layer, each of the second wiring lines includes a second metal layer formed on an interface with the insulation layer, and the first metal layer includes a metal material which is different from a metal material forming the second metal layer.

Abstract translation: 印刷布线板包括绝缘层，形成在绝缘层上并定位成连接电子部件的导电焊盘和包括第一和第二导电图案并形成在绝缘层上的导电布线图案，使得导电布线图案在 导电垫。 第一图案包括第一布线，第二图案包括第二布线，第一和第二导电图案形成为使得第一布线和第二布线交替排列在绝缘层上，每个第一布线包括 形成在与所述绝缘层的界面上的第一金属层，每个所述第二布线包括形成在与所述绝缘层的界面上的第二金属层，并且所述第一金属层包括与形成金属的金属材料不同的金属材料 第二金属层。

公开(公告)号：US20150223339A1

公开(公告)日：2015-08-06

申请号：US14685747

申请日：2015-04-14

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hideyo NAKAMURA ,  Masafumi HORIO

IPC: H05K1/18 ,  H05K7/20 ,  H01L23/31 ,  H05K1/02 ,  H01L23/00 ,  H01L25/07

CPC classification number: H05K1/181 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/49833 ,  H01L24/17 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/0212 ,  H05K1/0243 ,  H05K1/0296 ,  H05K3/3447 ,  H05K7/2089 ,  H05K2201/0364 ,  H05K2201/06 ,  H05K2201/09972 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor device, while being small, makes it possible to achieve low inductance responding to high speed switching. The semiconductor device includes a plurality of conductive pattern members, on each of which is mounted one or a plurality of power semiconductor chips, and a printed circuit board wherein a chip rod-form conductive connection member connected to the power semiconductor chip and a pattern rod-form conductive connection member connected to the conductive pattern member are disposed on the surface opposing the conductive pattern member. The conductive pattern member is formed of a narrow portion and a wide portion, the narrow portion of at least one conductive pattern member and the printed circuit board are connected by the pattern rod-form conductive connection member, and a current path is formed between the conductive pattern member and the power semiconductor chip connected via the chip rod-form conductive connection member to the printed circuit board.

Abstract translation: 半导体器件虽然小，但可以实现响应于高速开关的低电感。 半导体器件包括多个导电图案构件，每个导电图案构件安装有一个或多个功率半导体芯片，以及印刷电路板，其中连接到功率半导体芯片的芯片棒状导电连接构件和图案棒 连接到导电图案构件的导电连接构件设置在与导电图案构件相对的表面上。 导电图案构件由狭窄部分和宽部分形成，至少一个导电图案构件的窄部分和印刷电路板通过图案棒状导电连接构件连接，并且电流路径形成在 导电图案构件和通过芯片棒状导电连接构件连接到印刷电路板的功率半导体芯片。

公开(公告)号：US20150146395A1

公开(公告)日：2015-05-28

申请号：US14554598

申请日：2014-11-26

Applicant: LOTES Co., Ltd

Inventor： Ted Ju ,  Kai Tze Huang ,  Chien Chih Ho ,  Tien Chih Yu ,  Chin Chi Lin

IPC: H01B1/02 ,  H05K1/14 ,  H05K1/09 ,  H05K1/18

CPC classification number: H01B1/02 ,  H01B1/026 ,  H01R4/04 ,  H01R12/714 ,  H01R12/73 ,  H01R13/2414 ,  H05K1/09 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3457 ,  H05K2201/0364 ,  H05K2201/042 ,  H05K2201/10189 ,  H05K2201/10984 ,  H05K2201/10992 ,  H05K2203/0278 ,  H05K2203/0475 ,  H05K2203/0495 ,  Y10T428/256 ,  Y10T428/31678

Abstract: An electrically conductive material includes a liquid gallium alloy mixed with multiple solid particles, so as to form an electrically conductive material in which solid and liquid coexist. The electrically conductive material is disposed between and electrically connecting a first conductor and a second conductor. The first conductor is disposed on a first electronic element, and the second conductor is disposed on a second electronic element.

Abstract translation: 导电材料包括与多个固体颗粒混合的液体镓合金，以形成固体和液体共存的导电材料。 导电材料设置在电连接第一导体和第二导体之间。 第一导体设置在第一电子元件上，第二导体设置在第二电子元件上。

公开(公告)号：US08749009B2

公开(公告)日：2014-06-10

申请号：US13205526

申请日：2011-08-08

Applicant: Michael Eugene Young ,  Arjun Daniel Srinivas ,  Matthew R. Robinson ,  Alexander Chow Mittal

Inventor： Michael Eugene Young ,  Arjun Daniel Srinivas ,  Matthew R. Robinson ,  Alexander Chow Mittal

IPC: H01L31/00 ,  H01L31/048 ,  H01L31/0216

CPC classification number: H05K1/09 ,  H01L31/02167 ,  H01L31/0481 ,  H01L31/05 ,  H01L31/055 ,  H05K1/0274 ,  H05K1/0313 ,  H05K1/115 ,  H05K2201/0302 ,  H05K2201/0326 ,  H05K2201/0364 ,  H05K2201/10977 ,  Y02E10/52 ,  Y02E10/54 ,  Y02E10/542

Abstract: Active or functional additives are embedded into surfaces of host materials for use as components in a variety of electronic or optoelectronic devices, including solar devices, smart windows, displays, and so forth. Resulting surface-embedded device components provide improved performance, as well as cost benefits arising from their compositions and manufacturing processes.

Abstract translation: 活性或功能添加剂嵌入主体材料的表面，用作各种电子或光电子器件中的组件，包括太阳能装置，智能窗户，显示器等。 所得到的表面嵌入式设备组件提供了改进的性能，以及由其组成和制造过程产生的成本优势。

公开(公告)号：US11874988B2

公开(公告)日：2024-01-16

申请号：US17636098

申请日：2021-03-10

Applicant: Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hui Wen ,  Lianbin Liu ,  Xu Lu ,  Hengzhen Liang

IPC: G06F3/041 ,  H05K1/18

CPC classification number: G06F3/04164 ,  G06F3/0412 ,  H05K1/18 ,  H05K2201/0364 ,  H05K2201/10128

Abstract: Embodiments of the present disclosure provide a bonding circuit board, one end of which is connected to a display panel, and the other end of which is connected to a host side; the bonding circuit board includes a first sub-section and a second sub-section, which may be bonded and connected to each other, the first sub-section includes at least three first printed circuit layers, which are stacked on one another, and an insulation layer is arranged between any two adjacent first printed circuit layers of the at least three first printed circuit layers; and the second sub-section includes one second printed circuit layer or two second printed circuit layers which are stacked on each other, and the insulation layer is arranged between the two second printed circuit layers.

公开(公告)号：US11842958B2

公开(公告)日：2023-12-12

申请号：US17697937

申请日：2022-03-18

Applicant: Chun-Ming Lin

Inventor： Chun-Ming Lin

IPC: H05K1/09 ,  H05K1/11 ,  H01L23/498 ,  C25D7/12 ,  H01L21/48 ,  C25D3/38 ,  H05K1/18

CPC classification number: H01L23/49866 ,  C25D3/38 ,  C25D7/12 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/09 ,  H05K1/112 ,  H05K1/18 ,  H05K2201/0332 ,  H05K2201/0364 ,  H05K2201/095 ,  H05K2201/09509

Abstract: The present disclosure provides a multilayer wiring structure, including a plurality of dielectric layers, a plurality of conductive wiring layers interleaved with the plurality of dielectric layers, wherein the plurality of conductive wiring layers includes copper-phosphorous alloys (such as Cu3P).