公开(公告)号：US20160088741A1

公开(公告)日：2016-03-24

申请号：US14853125

申请日：2015-09-14

Applicant: Océ-Technologies B.V.

Inventor： Hendrikus J.T.M. VAN DEN BERSSELAAR

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/38 ,  H05K3/06

CPC classification number: H05K1/03 ,  H05K1/0298 ,  H05K3/0085 ,  H05K3/061 ,  H05K3/38 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2203/013

Abstract: A method of manufacturing a multi-layer printed circuit board by bonding together a plurality of circuit board layers, each of which includes a substrate and a conductive circuit pattern on at least one surface of the substrate, includes the steps of: coating the surface of the substrate with a continuous layer of conductive material, masking the layer with a resist, etching away a part of the conductive material so as to obtain the circuit pattern with conductive parts separated by gaps, and filling the gaps with an electrically insulating adhesive material to a level that is at least equal to the thickness of the layer of conductive material. The resist is left on the conductive parts and the adhesive material is selected to be chemically compatible with the resist.

Abstract translation: 一种多层印刷电路板的制造方法，其特征在于，在所述基板的至少一个表面上包含基板和导电电路图案的多个电路基板层粘合在一起，其特征在于，包括： 具有连续导电材料层的衬底，用抗蚀剂掩蔽该层，蚀刻掉导电材料的一部分，以获得具有由间隙分离的导电部件的电路图案，并用电绝缘粘合剂材料填充间隙 至少等于导电材料层的厚度的水平。 抗蚀剂留在导电部分上，并且粘合剂材料被选择为与抗蚀剂化学相容。

公开(公告)号：US20160088737A1

公开(公告)日：2016-03-24

申请号：US14806895

申请日：2015-07-23

Applicant: FUJITSU LIMITED

Inventor： Shinya Iijima ,  yoshikatsu ishizuki

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K3/3436 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/0367 ,  H05K2201/10984 ,  Y02P70/613

Abstract: An electronic device includes a resin layer, a conductive layer buried in the resin layer, an electronic part buried in the resin layer, and a wiring layer arranged on the resin layer, the wiring layer including wiring and an opening, the wiring being connected electrically to the conductive layer and the electronic part, the opening communicating with the conductive layer.

Abstract translation: 电子设备包括树脂层，埋在树脂层中的导电层，埋在树脂层中的电子部件和布置在树脂层上的布线层，布线层包括布线和开口，布线电连接 到导电层和电子部件，开口与导电层连通。

公开(公告)号：US09275967B2

公开(公告)日：2016-03-01

申请号：US14148482

申请日：2014-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Min Liang ,  Jiun-Yi Wu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/66

CPC classification number: H01L23/49838 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11614 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/17132 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/05042 ,  H01L2924/0533 ,  H01L2924/0534 ,  H01L2924/05342 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05994 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0353 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

Abstract translation: 提供了一个管芯和一个衬底。 芯片包括至少一个集成电路芯片，并且该基板包括至少部分延伸穿过其中的导电柱的第一和第二子集。 导电柱的第一子集中的每一个包括从衬底的表面突出的突出隆起焊盘，并且导电柱的第二子集各自部分地形成凹陷在衬底的表面内的迹线。 裸片经由多个导电凸块耦合到基板，每个导电凸块在突起凸块焊盘和模具中的一个之间延伸。

公开(公告)号：US09204530B2

公开(公告)日：2015-12-01

申请号：US13869553

申请日：2013-04-24

Applicant: PANASONIC CORPORATION

Inventor： Hiromitsu Takashita ,  Tsuyoshi Takeda ,  Yuko Konno ,  Hiroaki Fujiwara ,  Shingo Yoshioka

IPC: H05K7/00 ,  H05K1/02 ,  H01L23/498 ,  H01L21/56 ,  H05K3/36 ,  H01L25/065 ,  H01L23/00 ,  H01L23/66 ,  H01L25/10 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/0213 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6605 ,  H01L2224/02311 ,  H01L2224/0235 ,  H01L2224/0237 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32104 ,  H01L2224/32105 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32227 ,  H01L2224/32237 ,  H01L2224/32238 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/30111 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/112 ,  H05K1/114 ,  H05K3/323 ,  H05K3/368 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/09227 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/09381 ,  H05K2201/09427 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The present invention relates to electronic components assembly for electrically connecting electronic components to each other, wherein a wiring formed on a surface of a first electronic component and a wiring formed on a surface of a second electronic component face each other, and are bonded to each other with an electric conductor interposed therebetween, so as to electrically connect the first electronic component and the second electronic component. The electric conductor is a resin composition containing solder or conductive filler.

Abstract translation: 本发明涉及将电子部件彼此电连接的电子部件组件，其中形成在第一电子部件的表面上的布线和形成在第二电子部件的表面上的布线彼此面对，并且被接合到每个 另一个电导体插入其间，以便电连接第一电子部件和第二电子部件。 电导体是含有焊料或导电填料的树脂组合物。

公开(公告)号：US20150287615A1

公开(公告)日：2015-10-08

申请号：US14684427

申请日：2015-04-12

Applicant: Ananda H. Kumar ,  Ashish Athana ,  Farooq Quadri

Inventor： Ananda H. Kumar ,  Ashish Athana ,  Farooq Quadri

IPC: H01L21/48 ,  G01R31/26

CPC classification number: H01L21/486 ,  G01R1/0491 ,  G01R3/00 ,  G01R31/2601 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15312 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2203/308 ,  H01L2924/00 ,  H01L2924/00014

Abstract: This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of the semiconductor devices.

Abstract translation: 本文件描述了具有一层或多层内部厚膜金属导体图案的多层陶瓷衬底的制造和使用，其中与衬底的一个或两个主表面相交的任何或全部金属通孔延伸出 用于制造柔性，暂时或永久互连的表面到电子部件的端子。 这种结构对于半导体器件的晶片探测和封装是有用的。

公开(公告)号：US20150257262A1

公开(公告)日：2015-09-10

申请号：US14432278

申请日：2013-10-04

Applicant: LG INNOTEK CO., LTD.

Inventor： Sang Myung Lee ,  Byeong Ho Kim ,  Jae Seok Park ,  Yeong Uk Seo ,  Hyun Seok Seo ,  Chang Woo Yoo ,  Kyu Won Lee

IPC: H05K1/03 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0346 ,  H05K1/0298 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/115 ,  H05K1/119 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/4007 ,  H05K3/465 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/041

Abstract: A printed circuit board includes a core insulating layer including an isotropic resin, a first circuit pattern filled in a circuit pattern groove at an upper portion or a lower portion of the core insulating layer, a first insulating layer provided in a top surface thereof with a circuit pattern groove and covering the first circuit pattern, and a second circuit pattern to fill the circuit pattern groove of the first insulating layer. A material, such as polyimide, having an isotropic structure is employed for the core insulating layer, thereby preventing the substrate from being bent without glass fiber. Since the glass fiber is not included, the buried pattern is formed at the upper portion or the lower portion of the core insulating layer, so that the thin substrate is fabricated.

Abstract translation: 一种印刷电路板包括：包含各向同性树脂的芯绝缘层，填充在芯绝缘层的上部或下部的电路图形槽中的第一电路图案，在其顶表面上设置有第一绝缘层， 电路图案槽并覆盖第一电路图案，以及第二电路图案，以填充第一绝缘层的电路图案槽。 对于芯绝缘层使用具有各向同性结构的材料，例如聚酰亚胺，从而防止基板在没有玻璃纤维的情况下弯曲。 由于不包括玻璃纤维，因此在芯绝缘层的上部或下部形成掩埋图案，从而制造薄基板。

公开(公告)号：US09117883B2

公开(公告)日：2015-08-25

申请号：US13897480

申请日：2013-05-20

Applicant: The Boeing Company

Inventor： Keith Daniel Humfeld

IPC: H01L21/768 ,  H01L23/532 ,  H05K3/22 ,  B82Y30/00

CPC classification number: H05K3/222 ,  B82Y30/00 ,  H01L21/76838 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0367 ,  H05K2201/10363 ,  H01L2924/00

Abstract: A fabricated substrate has at least one plurality of posts. The plurality is fabricated such that the two posts are located at a predetermined distance from one another. The substrate is exposed to a fluid matrix containing functionalized carbon nanotubes. The functionalized carbon nanotubes preferentially adhere to the plurality of posts rather than the remainder of the substrate. A connection between posts of the at least one plurality of posts is induced by adhering one end of the functionalized nanotube to one post and a second end of the functionalized carbon nanotube to a second post.

Abstract translation: 制造的基板具有至少多个柱。 多个制造成使得两个柱彼此相隔预定距离。 将基底暴露于含有官能化碳纳米管的流体基质。 功能化的碳纳米管优先粘附到多个柱而不是衬底的其余部分。 通过将功能化纳米管的一端粘附到官能化碳纳米管的一个柱和第二端到第二柱来诱导至少一个多个柱的柱之间的连接。

公开(公告)号：US09105989B2

公开(公告)日：2015-08-11

申请号：US13867188

申请日：2013-04-22

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kei Murayama ,  Shinji Nakazawa ,  Miki Suzuki

IPC: H05K1/11 ,  H01R12/00 ,  H01R4/02 ,  H05K3/34 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01R9/095 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16237 ,  H01L2224/17051 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/12042 ,  H01L2924/381 ,  H01R4/02 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: A connection structure includes a column electrode; a first connecting portion connected to one end of the column electrode; and a second connecting portion connected to another end of the column electrode via solder, wherein a height of the column electrode is a width of the first connecting portion or greater.

Abstract translation: 连接结构包括列电极; 连接到所述列电极的一端的第一连接部分; 以及通过焊料与列电极的另一端连接的第二连接部，其中，所述列电极的高度为所述第一连接部的宽度以上。

公开(公告)号：US09082785B2

公开(公告)日：2015-07-14

申请号：US13616174

申请日：2012-09-14

Applicant: Yoshiyuki Ishida ,  Sadao Matsushima ,  Toshihide Fukuchi

Inventor： Yoshiyuki Ishida ,  Sadao Matsushima ,  Toshihide Fukuchi

IPC: H01P3/08 ,  H01L23/66 ,  H01L23/552 ,  H01L23/64 ,  H05K1/02 ,  H05K1/11 ,  H01P1/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/642 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/093 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09854 ,  H05K2201/10098 ,  H01L2924/00

Abstract: A high-frequency circuit board capable of easily forming a bias line whose resonance frequency is sufficiently separated from operating frequency is provided. On a high-frequency circuit board 100, by electrically connecting a bias line 11 to a high-frequency circuit 10 using blind via holes 106 and 107, it is possible to limit the route that has a possibility of producing resonance only to the bias line connecting the ends 106a and 107a of the blind via holes 106 and 107 to the bias line 11. By adjusting the route length from the end 106a to the end 107a, it is possible to prevent production of resonance in the vicinity of the operating frequency.

Abstract translation: 提供了能够容易地形成谐振频率与工作频率充分分离的偏置线的高频电路基板。 在高频电路板100上，通过使用盲通孔106和107将偏置线11与高频电路10进行电连接，可以限制仅具有产生谐振的可能性的路径到偏置线 将盲孔106和107的端部106a和107a连接到偏置线11.通过调整从端部106a到端部107a的路线长度，可以防止在工作频率附近产生谐振。

公开(公告)号：US20150163899A1

公开(公告)日：2015-06-11

申请号：US14625757

申请日：2015-02-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Hitoshi SAKAGUCHI ,  Wataru KANEDA ,  Masato TANAKA ,  Akio ROKUGAWA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0298 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/181 ,  H05K3/4007 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/025 ,  H01L2924/00

Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.

Abstract translation: 布线板依次包括在芯层上形成的第一绝缘层和第二绝缘层; 依次形成在芯层的另一表面上的第三绝缘层和阻焊层，分别形成在第一绝缘层和第二绝缘层中的第一布线层和第二布线层，其中第一绝缘层和第一绝缘层的第一端面 通过布线从最外侧的第一绝缘层的第一表面暴露出来，与最外层的第二布线层直接连接，第一通孔布线和最外层的第二布线层被分开地形成，最外面的第一绝缘层的第一表面和第一 第一通孔布线的端面是抛光表面，光滑的表面并且彼此齐平，并且第二布线层的布线密度高于第一布线层的布线密度。