公开(公告)号：US20110132640A1

公开(公告)日：2011-06-09

申请号：US13026965

申请日：2011-02-14

Applicant: Kazuhiro Kashiwakura

Inventor： Kazuhiro Kashiwakura

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0216 ,  H01L23/50 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K1/114 ,  H05K2201/09336 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.

Abstract translation: 公开了一种印刷线路板，其具有各自插在电源层和接地层之间的信号层，其中信号层包括用于接地电位的布线区域和用于电源电位的布线区域中的至少一个。

公开(公告)号：US07928816B2

公开(公告)日：2011-04-19

申请号：US12069763

申请日：2008-02-13

Applicant: Reddy R. Vangala

Inventor： Reddy R. Vangala

IPC: H01P9/00 ,  H01P1/201

CPC classification number: H01P1/2056 ,  H01P1/205 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09336 ,  H05K2201/1006 ,  H05K2201/10969

Abstract: A delay filter module comprising at least one dielectric boneblack ceramic band pass filter and a circuit for compensating/equalizing the signal delay produced by the delay filter. In one embodiment, the circuit is defined by a hybrid coupler defining at least two ports coupled to a dielectric ceramic reactive termination block defining at least a pair of reactive termination resonators and coupling capacitors. The delay can be adjusted by tuning the dielectric boneblack band pass filter and/or the reactive termination resonators and/or the coupling capacitors defined by the dielectric ceramic reactive termination block.

Abstract translation: 延迟滤波器模块，包括至少一个介质整体陶瓷带通滤波器和用于补偿/均衡由延迟滤波器产生的信号延迟的电路。 在一个实施例中，电路由限定了至少两个端口的混合耦合器限定，该至少两个端口耦合到限定至少一对电抗端接谐振器和耦合电容器的电介质陶瓷反应性端接块。 可以通过调谐电介质单块带通滤波器和/或由电介质陶瓷反应性端接块限定的反应性端接谐振器和/或耦合电容器来调节延迟。

公开(公告)号：US07919716B2

公开(公告)日：2011-04-05

申请号：US12580124

申请日：2009-10-15

Applicant: Kiyomi Muro ,  Gen Fukaya

Inventor： Kiyomi Muro ,  Gen Fukaya

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/0236 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: According to one embodiment, a printed wiring board includes an insulating layer, a first conductor pattern on the insulating layer configured to be a signal line, and a second conductor pattern on the insulating layer. The second conductor pattern includes a larger conductor area than the first conductor pattern, and a slit which allows the second conductor pattern to stretch to follow a thermal expansion of the insulating layer.

Abstract translation: 根据一个实施例，印刷布线板包括绝缘层，绝缘层上的构成为信号线的第一导体图案和绝缘层上的第二导体图案。 第二导体图案包括比第一导体图案更大的导体面积，以及允许第二导体图案拉伸以跟随绝缘层的热膨胀的狭缝。

公开(公告)号：US20110011637A1

公开(公告)日：2011-01-20

申请号：US12920426

申请日：2009-03-24

Applicant: Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

Inventor： Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

IPC: H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayer printed circuit board, including: a signal interconnection which transmits and receives an electrical signal between electronic components; a ground interconnection connected to a ground of a circuit; a power interconnection connected to a power layer to supply power to electronic components; at least one ground layer installed in an inner layer; at least one clearance which passes through the ground layer; and a ground via which connects the ground interconnection with the ground layer. The signal interconnection and the ground interconnection or the signal interconnection and the power interconnection are installed in a pair, and a pair of interconnection vias for interlayer connection are inserted through the clearance installed in the ground layer so that one of the pair of interconnection vias is connected to the ground layer by the ground interconnection.

Abstract translation: 一种多层印刷电路板，包括：在电子部件之间传输和接收电信号的信号互连; 连接到电路的地的接地互连; 连接到功率层以向电子部件供电的电力互连; 至少一个地层安装在内层中; 至少一个通过地层的间隙; 以及将接地互连与接地层连接的接地。 信号互连和接地互连，信号互连和电源互连成对安装，并且用于层间连接的一对互连通孔穿过安装在接地层中的间隙插入，使得一对互连通孔中的一个 通过地面互连连接到地层。

公开(公告)号：US20100181101A1

公开(公告)日：2010-07-22

申请号：US12686533

申请日：2010-01-13

Applicant: Jang Soon HAN ,  Seung Myen Lee

Inventor： Jang Soon HAN ,  Seung Myen Lee

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09772 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A printed circuit board (PCB) reduces a simultaneous switching noise (SSN) causing power noise, thereby reducing radiated electromagnetic interference (EMI). In a double-layered PCB, a first substrate is arranged in parallel with a second substrate while being spaced apart from the second substrate by a predetermined distance. The first substrate includes a ground plane, which is deposited over an entirety of the first substrate. The second substrate includes a power plane deposited at a position of a component mounted to the printed circuit board (PCB) to transmit power to the component. Thus, the power trace of the PCB is simplified in structure, thereby reducing EMI radiation noise.

Abstract translation: 印刷电路板（PCB）降低了产生电源噪声的同时开关噪声（SSN），从而降低了辐射电磁干扰（EMI）。 在双层PCB中，第一衬底与第二衬底平行地布置，同时与第二衬底隔开预定距离。 第一衬底包括沉积在整个第一衬底上的接地平面。 第二基板包括沉积在安装到印刷电路板（PCB）上的部件的位置以将功率传递到部件的电源平面。 因此，PCB的电源轨迹在结构上简化，从而降低EMI辐射噪声。

公开(公告)号：US07742315B2

公开(公告)日：2010-06-22

申请号：US11282041

申请日：2005-11-17

Applicant: Wiren D. Becker ,  Bruce J. Chamberlin ,  Gerald J. Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

Inventor： Wiren D. Becker ,  Bruce J. Chamberlin ,  Gerald J. Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/11 ,  H01R12/523 ,  H01R13/6466 ,  H01R13/6471 ,  H01R13/6589 ,  H01R13/6625 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/10189

Abstract: The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

Abstract translation: 本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。 特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。 为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容 在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

公开(公告)号：US07635814B2

公开(公告)日：2009-12-22

申请号：US11941979

申请日：2007-11-19

Applicant: Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

Inventor： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10S439/941

Abstract: A printed circuit board (PCB) includes first and second signal layers sandwiching a dielectric layer therebetween and a first differential pair and a second differential pair each having a positive differential trace and a negative differential trace. The positive differential traces of the two differential pairs are disposed within the first signal layer. The negative differential traces of the two differential pairs are disposed within the second signal layer. The positive differential trace of the first differential pair is defined at the left side of the positive differential trace of the second differential pair. The negative differential trace of the first differential pair is defined at the right side of the negative differential trace of the second differential pair.

Abstract translation: 印刷电路板（PCB）包括夹在其间的电介质层的第一和第二信号层，以及分别具有正差分迹线和负差分迹线的第一差分对和第二差分对。 两个差分对的正差分迹线设置在第一信号层内。 两个差分对的负差分迹线设置在第二信号层内。 第一差分对的正差分迹线被定义在第二差分对的正差分迹线的左侧。 第一差分对的负差分迹线被限定在第二差分对的负差分迹线的右侧。

公开(公告)号：US20090260860A1

公开(公告)日：2009-10-22

申请号：US12211057

申请日：2008-09-15

Applicant: YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU

Inventor： YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0245 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/0969 ,  Y10T29/49156

Abstract: An exemplary FPCB includes two or more dielectric layers. Each dielectric layer is located between a signal layer and a ground layer. A differential pair including two transmission lines is arranged in each signal layer. Each ground layer includes one or more voids defined therein. Each void is opposite and adjacent to a differential pair.

Abstract translation: 示例性FPCB包括两个或更多个电介质层。 每个电介质层位于信号层和接地层之间。 在每个信号层中布置包括两条传输线的差分对。 每个接地层包括其中限定的一个或多个空隙。 每个空隙与差分对相反并相邻。

公开(公告)号：US20090256253A1

公开(公告)日：2009-10-15

申请号：US12490872

申请日：2009-06-24

Applicant: Francesco Preda ,  Lloyd A. Walls

Inventor： Francesco Preda ,  Lloyd A. Walls

IPC: H01L23/12 ,  H01L21/50 ,  G06F17/50

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Abstract translation: 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所得到的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

公开(公告)号：US20090255723A1

公开(公告)日：2009-10-15

申请号：US12103191

申请日：2008-04-15

Applicant: Hui-Lung LAI

Inventor： Hui-Lung LAI

IPC: H05K1/00

CPC classification number: H05K1/0219 ,  G06F3/044 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09263 ,  H05K2201/09336 ,  H05K2201/097

Abstract: A printed circuit board with ground grid includes a first insulating plate, a plurality of first metal lines formed on the first insulating plate, a sub-circuit board above the plurality of first metal lines, a second insulating plate above the sub-circuit board, a plurality of second metal lines formed on the second insulating plate, and, a plurality of conductive components formed in and through the second insulating plate and the sub-circuit board to electrically connect the plurality of first metal lines and the plurality of second metal lines. As additional electronic elements and circuits can be located on the first insulating plate and/or on the second insulating plate without limitation, difficulties for printed circuit board layout can be dramatically reduced.

Abstract translation: 具有接地栅格的印刷电路板包括第一绝缘板，形成在第一绝缘板上的多个第一金属线，多个第一金属线上方的副电路板，副电路板上方的第二绝缘板， 形成在所述第二绝缘板上的多个第二金属线，以及形成在所述第二绝缘板中的多个导电部件和所述副电路基板，以将所述多个第一金属线和所述多个第二金属线 。 由于附加的电子元件和电路可以无限制地位于第一绝缘板和/或第二绝缘板上，所以印刷电路板布局的困难可以大大降低。