公开(公告)号：US20100038122A1

公开(公告)日：2010-02-18

申请号：US12540721

申请日：2009-08-13

Applicant: Kaoru SAKINADA ,  Yasuyuki ODA

Inventor： Kaoru SAKINADA ,  Yasuyuki ODA

IPC: H05K1/18 ,  B23K37/00

CPC classification number: H05K1/144 ,  H01L23/10 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/19105 ,  H03H9/0542 ,  H03H9/0547 ,  H03H9/1071 ,  H05K2201/042 ,  H05K2201/09354 ,  H05K2201/10083 ,  H05K2201/10674 ,  H05K2201/10969 ,  H05K2203/1147 ,  H01L2224/0401

Abstract: An electronic component module includes: an insulative substrate; a device chip mounted on a first surface of the insulative substrate in flip-chip mounting; a chip component connected to the insulative substrate; a lid provided above the insulative substrate and the device chip; a first metal pattern that is provided in edge portions on the first surface of the insulative substrate so as to surround the first surface of the insulative substrate; a second metal pattern that is provided in edge portions on a second surface of the lid opposite to the first surface so as to surround the second surface; and seal solder joining the first and second metal patterns so as to define a cavity that is formed in a region that is located between the insulative substrate and the lid and is not provided with the first and second metal patterns and is further formed between the insulative substrate and the device chip.

Abstract translation: 电子部件模块包括：绝缘基板; 以倒装芯片安装在所述绝缘基板的第一表面上安装的器件芯片; 连接到所述绝缘基板的芯片部件; 设置在所述绝缘基板和所述器件芯片上方的盖; 第一金属图案，设置在绝缘基板的第一表面上的边缘部分中，以围绕绝缘基板的第一表面; 第二金属图案，设置在与第一表面相对的第二表面上的边缘部分中，以围绕第二表面; 以及密封焊料，其接合第一和第二金属图案，以便限定形成在位于绝缘基板和盖之间的区域中并且没有设置第一和第二金属图案并且进一步形成在绝缘体之间的空腔 基板和器件芯片。

公开(公告)号：US20090279038A1

公开(公告)日：2009-11-12

申请号：US12387982

申请日：2009-05-11

Applicant: De-Ching Shie

Inventor： De-Ching Shie

IPC: G02F1/1345

CPC classification number: G02F1/1345 ,  G02F1/13452 ,  G02F2001/13456 ,  H05K1/0259 ,  H05K3/361 ,  H05K2201/09354

Abstract: A liquid crystal panel includes a signal transmission section and a flexible printed circuit (FPC). The signal transmission section includes electrical conductive terminals. The FPC includes an insulating film and conductive lines disposed on a first surface of the insulating film. The conductive lines are electrically connected to the electrical conductive terminals. The insulating film substantially covers the electrical conductive terminals.

Abstract translation: 液晶面板包括信号传输部分和柔性印刷电路（FPC）。 信号传输部分包括导电端子。 FPC包括绝缘膜和布置在绝缘膜的第一表面上的导电线。 导线与导电端子电连接。 绝缘膜基本上覆盖导电端子。

公开(公告)号：US07606018B2

公开(公告)日：2009-10-20

申请号：US11488660

申请日：2006-07-19

Applicant: Koichi Ishii ,  Yuji Terada ,  Takeshi Yanata

Inventor： Koichi Ishii ,  Yuji Terada ,  Takeshi Yanata

IPC: H02H1/04 ,  H01F5/04 ,  H01F27/28

CPC classification number: H02H9/005 ,  H03H7/0107 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/38 ,  H03H2001/0085 ,  H05K1/0239 ,  H05K1/0254 ,  H05K1/0298 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/09263 ,  H05K2201/09354 ,  H05K2201/10022

Abstract: A surge absorbing circuit has a substrate on which a first conductor, a second conductor, and a third conductor are placed, and a surge absorber having a first terminal and a second terminal. The first conductor and the second conductor are mutually coupled in a polarity-reversed relation. One end of the first conductor is connected to one end of the second conductor. The third conductor is electrically isolated from the first conductor and the second conductor on the substrate. The first terminal of the surge absorber is connected to a connection portion between the first conductor and the second conductor. The second terminal of the surge absorber is connected to the third conductor.

Abstract translation: 浪涌吸收电路具有其上放置有第一导体，第二导​​体和第三导体的基板，以及具有第一端子和第二端子的浪涌吸收器。 第一导体和第二导体以极性反转的关系相互耦合。 第一导体的一端连接到第二导体的一端。 第三导体与衬底上的第一导体和第二导体电隔离。 浪涌吸收器的第一端子连接到第一导体和第二导体之间的连接部分。 浪涌吸收器的第二端子连接到第三导体。

公开(公告)号：US20090015993A1

公开(公告)日：2009-01-15

申请号：US11948547

申请日：2007-11-30

Applicant: CHING-SEN TSAI ,  MEI-TSU TSAO ,  CHENG-LUNG CHANG

Inventor： CHING-SEN TSAI ,  MEI-TSU TSAO ,  CHENG-LUNG CHANG

IPC: G06F1/16 ,  H01R4/66 ,  H02H9/04

CPC classification number: H05K9/0067 ,  H05K1/0215 ,  H05K1/0393 ,  H05K2201/09354

Abstract: A grounding apparatus (200) includes at least one conductive member (20), a sliding mechanism (30) and a flexible printed circuit board (40). The sliding mechanism is conductive and electrically connected to the conductive member. The flexible printed circuit board includes a conductive layer (421) and a grounding end (4231), the conductive layer and the grounding end are electrically connected to the sliding mechanism.

Abstract translation: 接地装置（200）包括至少一个导电构件（20），滑动机构（30）和柔性印刷电路板（40）。 滑动机构是导电的并且电连接到导电构件。 柔性印刷电路板包括导电层（421）和接地端（4231），导电层和接地端电连接到滑动机构。

公开(公告)号：US07448132B2

公开(公告)日：2008-11-11

申请号：US11537754

申请日：2006-10-02

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/10

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：US20060121732A1

公开(公告)日：2006-06-08

申请号：US11334172

申请日：2006-01-18

Applicant: Xiaowei Yao ,  Tam Nguyen ,  Marc Finot ,  Rickie Lake ,  Jeffrey Bennett ,  Robert Kohler

Inventor： Xiaowei Yao ,  Tam Nguyen ,  Marc Finot ,  Rickie Lake ,  Jeffrey Bennett ,  Robert Kohler

IPC: H01L21/44 ,  H01L23/12 ,  H01L23/34 ,  H01L23/053

CPC classification number: H01L23/498 ,  C25D5/02 ,  H01L21/4846 ,  H01L23/10 ,  H01L23/15 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/241 ,  H05K3/243 ,  H05K2201/09354 ,  H01L2924/00

Abstract: A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.

Abstract translation: 电路封装包括具有开口的基板和适于有效散发热量的单个整体式散热器，其位于开口中以暴露与基板的顶表面和底表面共面的顶表面和底表面。 选择性电镀包括将第一和第二金属图案施加到基板表面，产生第一金属图案和金属源之间的电位差，并且通过将第一金属类型吸引到第一金属图案的电压电位来镀覆第一金属图案 。 第一金属图案的电压电位小于金属源的电压电位。

公开(公告)号：US06940730B1

公开(公告)日：2005-09-06

申请号：US10636365

申请日：2003-08-07

Applicant: Robin Berg, Jr. ,  Todd Husom ,  Derek Sayres

Inventor： Robin Berg, Jr. ,  Todd Husom ,  Derek Sayres

IPC: H04Q1/02 ,  H04Q1/10 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K7/14 ,  H05K7/18

CPC classification number: H04Q1/10 ,  H04Q1/023 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K1/18 ,  H05K7/1425 ,  H05K7/186 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract translation: 公开了一种底盘和相关通信电路卡。 底盘具有散热和阻燃特征，同时容纳高密度的电路卡。 实施例包括具有双层中间层的内壳，其将底盘分成顶部和底部室。 每个层具有部分对准的槽，并且在两层之间提供气隙。 实施例还包括在两个网格层之间具有气隙的双层网状覆盖物。 在内壳体的内表面上设置突起和凹槽，以接收在一个边缘上具有引导件的电路卡和另一边缘上的翅片。 电路卡包括导体结构，例如具有配对和分离的导体的多个板层。 电路卡还包括定位成与底盘的通风特征配合的一些组件，并且包括一些选择用于低功耗或降低可燃性的组件。

公开(公告)号：US20050039947A1

公开(公告)日：2005-02-24

申请号：US10949290

申请日：2004-09-27

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K1/02 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

Abstract translation: 提供了一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的配线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

公开(公告)号：US20040090748A1

公开(公告)日：2004-05-13

申请号：US10695463

申请日：2003-10-28

Applicant: KONICA MINOLTA HOLDINGS, INC

Inventor： Tadao Kishimoto ,  Yutaka Igarashi ,  Hironobu Hirayama

IPC: H05K007/20

CPC classification number: H05K1/0234 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/325 ,  H05K3/429 ,  H05K7/142 ,  H05K9/0039 ,  H05K2201/09354 ,  H05K2201/09618 ,  H05K2201/10022 ,  H05K2201/10409 ,  H05K2201/10446 ,  Y10T29/49155

Abstract: There is described a multi-layer printed circuit board and a method of installing it. The circuit board includes a first signal layer formed on its obverse surface; a ground layer arranged at a position next to the first signal layer; an electronic power source layer arranged at a position next to the ground layer; and a second signal layer formed on its reverse surface. The first and second patterns are formed around peripheral areas of the first and second signal layers, respectively. The first ground pattern and the second ground pattern are electrically coupled to each other by plural through holes, and the multi-layer printed circuit board is installed on an electro-conductive housing in such a manner that a substantially whole area of the second ground pattern electrically contacts a mounting area of the electro-conductive housing, the mounting area being an electro-conductive area continuously coupled to the electro-conductive housing.

Abstract translation: 描述了一种多层印刷电路板及其安装方法。 电路板包括在其正面上形成的第一信号层; 布置在与所述第一信号层相邻的位置处的接地层; 布置在接地层旁边的位置处的电子电源层; 以及形成在其反面上的第二信号层。 第一和第二图案分别形成在第一和第二信号层的周边区域周围。 第一接地图案​​和第二接地图案通过多个通孔彼此电耦合，并且多层印刷电路板以这样的方式安装在导电外壳上，使得第二接地图案的大致整个区域 电接触导电壳体的安装区域，该安装区域是连续耦合到导电壳体的导电区域。

公开(公告)号：US06379159B1

公开(公告)日：2002-04-30

申请号：US09541898

申请日：2000-04-03

Applicant: Kazunori Mune ,  Kazuo Ouchi ,  Satoshi Tanigawa ,  Hirofumi Fujii

Inventor： Kazunori Mune ,  Kazuo Ouchi ,  Satoshi Tanigawa ,  Hirofumi Fujii

IPC: H05G336

CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/423 ,  H05K2201/09354 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: In a method for manufacturing an interposer for CSP and its intermediate body, a first insulating layer is formed on a cathode substrate. An opening is formed at a position in the insulating layer where a contact is to be formed so that the surface of the substrate is exposed to the inner bottom of the opening. The opening is filled with metal by the electroplating using the cathode substrate as a cathode to form a conductive path. A circuit pattern which is contact with the conductive path is formed on the insulating layer. The cathode substrate is removed partially or entirely so that the end surface of the conductive path is exposed to form a contact. This permits a variation of the heights of a plurality of contacts to be reduced.

Abstract translation: 在制造CSP及其中间体用插入体的方法中，在阴极基板上形成第一绝缘层。 在要形成接触的绝缘层中的一个位置处形成开口，使得基板的表面暴露于开口的内底部。 通过使用阴极基板作为阴极的电镀，用金属填充开口以形成导电路径。 在绝缘层上形成与导电路径接触的电路图案。 部分或全部去除阴极基板，使得导电路径的端面暴露以形成接触。 这允许减少多个触点的高度的变化。