公开(公告)号：US09345136B1

公开(公告)日：2016-05-17

申请号：US14716452

申请日：2015-05-19

Applicant: SK hynix Inc.

Inventor： Seung Jee Kim ,  Won Duck Jung

IPC: H05K1/02 ,  H05K1/11 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15313 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09472 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A package substrate includes a core layer, first external interconnection lines on a top surface of the core layer, and internal interconnection lines. The first external interconnection lines include a first outermost external interconnection line on an edge of the core layer, and the internal interconnection lines include an outermost internal interconnection line in the edge of the core layer. A first bonding pad is disposed on the first outermost external interconnection line and exposed in a first bonding region of the core layer. A second bonding pad is disposed on the outermost internal interconnection line and exposed in a second bonding region of the core layer. The first bonding region is spaced apart from a chip attachment region by a first distance, and the second bonding region is spaced apart from the chip attachment region by a second distance greater than the first distance.

Abstract translation: 封装基板包括芯层，芯层顶表面上的第一外部互连线和内部互连线。 第一外部互连线包括在芯层的边缘上的第一最外部外部互连线，并且内部互连线包括在芯层的边缘中的最外部的内部互连线。 第一接合焊盘设置在第一最外部外部互连线上并暴露在芯层的第一接合区域中。 第二接合焊盘设置在最外部的内部互连线上并暴露在芯层的第二接合区域中。 第一接合区域与芯片连接区域间隔开第一距离，并且第二接合区域与芯片连接区域间隔开大于第一距离的第二距离。

公开(公告)号：US09332642B2

公开(公告)日：2016-05-03

申请号：US14481188

申请日：2014-09-09

Applicant: Panasonic Corporation

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/10 ,  H05K3/18 ,  H05K3/40 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/119 ,  H01L2224/81385 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/0076 ,  H05K3/0079 ,  H05K3/0085 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0224 ,  H05K2201/0233 ,  H05K2201/0239 ,  H05K2201/0376 ,  H05K2201/0769 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09972 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/0143 ,  H05K2203/0228 ,  H05K2203/0264 ,  H05K2203/0285 ,  H05K2203/0565 ,  H05K2203/0706 ,  H05K2203/0776 ,  H05K2203/1163 ,  Y02P70/611

Abstract: One aspect of the present invention relates to a circuit board including an insulating base substrate; and a circuit layer that is formed of a conductor and that is provided on the surface of the insulating base substrate, wherein the insulating base substrate has a smooth surface having a surface roughness Ra of 0.5 μm or less, and the conductor is at least partially embedded in a wiring groove formed in the surface of the insulating base substrate.

Abstract translation: 本发明的一个方面涉及一种包括绝缘基底的电路板; 以及电路层，其由导体形成，并且设置在所述绝缘基底基板的表面上，其中所述绝缘基底具有表面粗糙度Ra为0.5μm以下的平滑表面，并且所述导体至少部分地 嵌入形成在绝缘性基板的表面的布线槽。

公开(公告)号：US20160029492A1

公开(公告)日：2016-01-28

申请号：US14771512

申请日：2014-01-31

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Nozomu HIKINO ,  Hiroyuki TAKEBE

IPC: H05K3/00 ,  H04M1/02 ,  H05K1/03 ,  H05K1/11 ,  B29C45/14 ,  B29C45/16

CPC classification number: H05K3/0014 ,  B29C45/14 ,  B29C45/16 ,  B29C45/1671 ,  B29C2045/0079 ,  B29C2045/1687 ,  B29K2055/02 ,  B29K2069/00 ,  B29L2009/00 ,  B29L2031/3456 ,  B29L2031/3481 ,  H01Q1/243 ,  H04M1/0202 ,  H04M1/0249 ,  H05K1/0284 ,  H05K1/032 ,  H05K1/119 ,  H05K1/165 ,  H05K3/36 ,  H05K2201/09018 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/0999 ,  H05K2201/10098 ,  H05K2201/10265 ,  H05K2201/2036 ,  H05K2203/1322 ,  H05K2203/1476

Abstract: A first resin layer (1) has: a covered region which is covered by a second resin layer (2) and an exposed region (1a); a contact part (1b) which is provided in the exposed region (1a); and a bend part (1c) which is provided between (a) a boundary between the covered region and the exposed region (1a) and (b) the contact part (1b).

Abstract translation: 第一树脂层（1）具有被第二树脂层（2）和暴露区域（1a）覆盖的被覆区域。 设置在所述露出区域（1a）中的接触部（1b） 以及设置在（a）被覆盖区域与露出区域（1a）之间的边界和（b）接触部分（1b）之间的弯曲部分（1c）。

公开(公告)号：US09247644B2

公开(公告)日：2016-01-26

申请号：US14329062

申请日：2014-07-11

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro Kaneko ,  Kazuhiro Kobayashi ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Shunichiro Matsumoto ,  Ruofan Tang

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/00 ,  H05K7/10 ,  H05K1/11 ,  H05K3/34 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K1/113 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/2072 ,  H05K2203/0152 ,  H05K2203/0307 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/1184 ,  H05K2203/308

Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.

Abstract translation: 布线基板包括绝缘层，焊盘和阻焊层。 绝缘层具有形成有第一凹部的第一表面。 衬垫嵌入第一凹部。 垫包括第二表面和第三表面。 所述第三表面位于比所述第一表面更低的位置处，以暴露所述第一凹部的内壁表面。 垫在第三表面的中心部分形成有第二凹部。 阻焊层设置在第一表面上。 所述第一表面与所述第一凹部的周边部分的相邻部分的粗糙度小于所述第一表面的相邻部分的周边的第一表面的区域。

公开(公告)号：US20150342045A1

公开(公告)日：2015-11-26

申请号：US14718094

申请日：2015-05-21

Applicant: NICHIA CORPORATION

Inventor： Takuya NAKABAYASHI ,  Akira HORI

IPC: H05K1/11 ,  H05K1/18 ,  F21V8/00

CPC classification number: H05K1/111 ,  G02B6/0066 ,  G02B6/0073 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/10454 ,  H05K2203/048 ,  Y02P70/611

Abstract: A semiconductor device mounting structure includes a semiconductor device and a mounting substrate. The semiconductor device includes a first external connection terminal and a device-side mounting insulating region. The first external connection terminal is provided at a first end and has a metal region on a semiconductor mounting surface of the semiconductor device. The device-side mounting insulating region is defined by the metal region on the semiconductor mounting surface. The semiconductor mounting surface faces a substrate mounting surface. The mounting substrate has on the substrate mounting surface a land pattern made of an electrically conductive material to be electrically connected to the first external connection terminal. The land pattern is provided in a first shape to surround the device-side mounting insulating region and includes a land-side insulating region which has a second shape to correspond to a periphery of the device-side mounting insulating region.

Abstract translation: 半导体器件安装结构包括半导体器件和安装基板。 半导体器件包括第一外部连接端子和器件侧安装绝缘区域。 第一外部连接端子设置在第一端，并且在半导体器件的半导体安装表面上具有金属区域。 器件侧安装绝缘区域由半导体安装表面上的金属区域限定。 半导体安装表面面向基板安装表面。 安装基板在基板安装表面上具有由导电材料制成的焊盘图案，以电连接到第一外部连接端子。 所述焊盘图案设置成围绕所述器件侧安装绝缘区域的第一形状，并且包括具有与所述器件侧安装绝缘区域的周边相对应的第二形状的焊盘侧绝缘区域。

公开(公告)号：US09165814B2

公开(公告)日：2015-10-20

申请号：US14242156

申请日：2014-04-01

Applicant: ASML Netherlands B.V.

Inventor： Alexander Petrus Hilbers ,  Ronald Van Der Wilk

IPC: H01L21/683 ,  H05K1/02 ,  G03F7/20 ,  H05K3/40

CPC classification number: H01L21/6833 ,  G03F7/70066 ,  G03F7/70708 ,  G03F7/70991 ,  H05K1/0256 ,  H05K3/4007 ,  H05K2201/09472

Abstract: An electrical connector comprises a high voltage pad and a high voltage plate. When connected to another electrical connector, the two plates, which are at the same voltage as the pads, form a region of high voltage in which the field is low. The pads are positioned in that region. An electrostatic clamp of an EUV lithographic apparatus may have such a pad and plate, for connecting to the electrical connector. By placing the interconnection in a low field region, triple points (points of contact between a conductor, a solid insulator and a gas) may be present in that region.

Abstract translation: 电连接器包括高压焊盘和高压板。 当连接到另一个电连接器时，与焊盘处于相同电压的两个板形成场中低电压的区域。 垫位于该区域。 EUV光刻设备的静电夹具可以具有用于连接到电连接器的垫和板。 通过将互连置于低场区域中，可以在该区域中存在三个点（导体，固体绝缘体和气体之间的接触点）。

公开(公告)号：US09107316B2

公开(公告)日：2015-08-11

申请号：US14023740

申请日：2013-09-11

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H05K1/00 ,  H05K1/11 ,  G06F3/044 ,  H05K1/09 ,  H05K3/12 ,  H05K3/46

CPC classification number: H05K1/117 ,  G06F3/044 ,  H05K1/092 ,  H05K3/1258 ,  H05K3/4611 ,  H05K2201/0919 ,  H05K2201/09472 ,  H05K2201/09709 ,  H05K2201/09845

Abstract: A multi-layer micro-wire structure includes a substrate having a substrate edge. A first layer is formed over the substrate extending to a first layer edge. One or more first micro-channels are imprinted in the first layer, at least one imprinted first micro-channel having a micro-wire forming at least a portion of an exposed first connection pad in the first layer. A second layer is formed over the first layer extending to a second layer edge. One or more second micro-channels are imprinted in the second layer, at least one imprinted second micro-channel having a micro-wire forming at least a portion of an exposed second connection pad in the second layer. The second-layer edge is farther from the substrate edge than the first-layer edge for at least a portion of the second-layer edge so that the first connection pads are exposed through the second layer.

Abstract translation: 多层微线结构包括具有基板边缘的基板。 第一层形成在延伸到第一层边缘的衬底上。 一个或多个第一微通道被印在第一层中，至少一个压印的第一微通道具有在第一层中形成暴露的第一连接焊盘的至少一部分的微线。 在延伸到第二层边缘的第一层上形成第二层。 一个或多个第二微通道被印在第二层中，至少一个压印的第二微通道具有在第二层中形成暴露的第二连接焊盘的至少一部分的微线。 对于第二层边缘的至少一部分，第二层边缘比第一层边缘离基板边缘更远，使得第一连接焊盘通过第二层曝光。

公开(公告)号：US20150223330A1

公开(公告)日：2015-08-06

申请号：US14561540

申请日：2014-12-05

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kiyoshi OI ,  Takashi KURIHARA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/113 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K3/3436 ,  H05K3/4661 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2201/10674

Abstract: A wiring substrate includes a first multi-layer wiring layer having a stacked via structure including a first electrode pad, a second multi-layer wiring layer rinsing a non-stacked via structure including a second electrode pad. The second electrode pad is formed on an uppercut first insulating layer. The first electrode pad is formed on a second insulating layer which is located to a position lower by one layer than the first insulating layer, and the first electrode pad is arranged in an opening portion of the first insulating layer such that the upper face and the side face of the first electrode pad are exposed.

Abstract translation: 布线基板包括具有层叠通孔结构的第一多层布线层，包括第一电极焊盘，漂洗包括第二电极焊盘的非堆叠通孔结构的第二多层布线层。 第二电极焊盘形成在上切第一绝缘层上。 第一电极焊盘形成在位于比第一绝缘层低一层的位置的第二绝缘层上，第一电极焊盘设置在第一绝缘层的开口部分中，使得上表面和 露出第一电极焊盘的侧面。

公开(公告)号：US20150216050A1

公开(公告)日：2015-07-30

申请号：US14680463

申请日：2015-04-07

Applicant: IBIDEN CO., LTD.

Inventor： Satoru KAWAI ,  Kenji Sakai ,  Liyi Chen

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/34 ,  H05K1/02

CPC classification number: H05K1/112 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81192 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/032 ,  H05K1/113 ,  H05K3/205 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/0361 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A printed wiring board includes a resin insulation layer having a first surface and a second surface on an opposite side of the first surface, the resin insulation layer having an opening for a via conductor, a pad formed on the first surface of the resin insulation layer and provided to mount an electronic component, a conductive circuit formed on the second surface of the resin insulation layer, and a via conductor formed in the opening and connecting the pad and the conductive circuit. The pad has an embedded portion embedded in the resin insulation layer and a protruding portion protruding from the resin insulation layer, and the embedded portion has an external shape which is greater than an external shape the protruding portion.

Abstract translation: 印刷电路板包括树脂绝缘层，该树脂绝缘层具有在第一表面的相对侧上的第一表面和第二表面，树脂绝缘层具有用于通路导体的开口，形成在树脂绝缘层的第一表面上的焊盘 并且提供用于安装电子部件，形成在树脂绝缘层的第二表面上的导电电路和形成在开口中并连接焊盘和导电电路的通孔导体。 垫具有嵌入在树脂绝缘层中的嵌入部分和从树脂绝缘层突出的突出部分，并且嵌入部分具有大于突出部分的外部形状的外部形状。

公开(公告)号：US09070393B2

公开(公告)日：2015-06-30

申请号：US14196363

申请日：2014-03-04

Applicant: PANASONIC CORPORATION

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H01L23/04 ,  G11B5/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/14

CPC classification number: G11B5/486 ,  H01L21/4846 ,  H01L21/565 ,  H01L22/12 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49866 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82385 ,  H01L2224/82399 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/386 ,  H01L2924/3862 ,  H05K1/111 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2203/1461 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 本发明的一个方面是一种三维结构，其中在表面上形成布线，所述三维结构具有绝缘树脂层，所述绝缘树脂层含有由选自典型非金属元素中的至少一种元素形成的填料和 典型的金属元件，其中在绝缘树脂层的表面上形成用于布线的凹槽，并且布线导体的至少一部分嵌入到凹槽中用于布线。