公开(公告)号：US20110039427A1

公开(公告)日：2011-02-17

申请号：US12741108

申请日：2009-04-24

Applicant: Masanori Mizoguchi

Inventor： Masanori Mizoguchi

IPC: H01R12/00

CPC classification number: H05K3/326 ,  H01R12/718 ,  H05K1/118 ,  H05K1/147 ,  H05K3/306 ,  H05K3/363 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/091 ,  H05K2201/0949 ,  H05K2201/10378 ,  H05K2201/1059

Abstract: A female connector which is useful for space saving and height reduction of a connector connection portion is a female connector including: an insulating film having flexibility; a plurality of pad portions formed at predetermined positions on one face of the insulating film in an arranged manner; female terminal portions composed of openings formed at one lateral portions within faces of the pad portions so as to extend up to the other face of the insulating film; and spacer bumps formed at positions corresponding to the other lateral positions within the faces of the pad portions in a standing manner within the other face of the insulating film, proximal portions of the spacer bumps being electrically connected to the pad portions.

Abstract translation: 用于连接器连接部分的节省空间和降低高度的阴连接器是阴连接器，包括：具有柔性的绝缘膜; 以排列的方式形成在所述绝缘膜的一个表面上的预定位置处的多个焊盘部分; 阴端子部分由形成在焊盘部分的表面内的一个侧部处的开口组成，以延伸到绝缘膜的另一个面; 以及在所述绝缘膜的另一个表面内以垂直方式形成在与所述焊盘部分的所述表面内的其它侧向位置对应的位置处的间隔凸块，所述间隔件凸块的近侧部分电连接到所述焊盘部分。

公开(公告)号：US20100038803A9

公开(公告)日：2010-02-18

申请号：US11930210

申请日：2007-10-31

Applicant: Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L23/52

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Abstract translation: 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US20090316409A1

公开(公告)日：2009-12-24

申请号：US12457803

申请日：2009-06-22

Applicant: Yu-Sik Kim ,  Woo-Sung Han

Inventor： Yu-Sik Kim ,  Woo-Sung Han

IPC: F21S4/00 ,  F21V19/00 ,  H01J9/24

CPC classification number: H05K1/0295 ,  H01L25/0753 ,  H01L2224/16225 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/0949 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2203/173

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, the sub-mount including a base substrate including a first surface and a second surface different from the first surface, a conductive pattern on the first surface, a first pair and a second pair of first and second electrodes on the second surface, and vias extending through the base substrate between the first and second surfaces, wherein the conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes of the first and second pair of first and second electrodes through the vias.

Abstract translation: 一种用于可安装在其上的装置的AC和DC操作的子安装座，所述子安装件包括基底基板，所述基底基板包括第一表面和与所述第一表面不同的第二表面，所述第一表面上的导电图案， 在第二表面上的第二对第一和第二电极以及在第一和第二表面之间延伸通过基底基板的通孔，其中导电图案包括第一组安装部分和沿着第一对之间的第一电路径的两个通孔部分 的第一和第二电极，以及第二组安装部分和沿着第二对电极之间的第二电气路径的两个通孔部分，所述通孔部分将导电图案的各个部分连接到第一和第二电极的相应电极 一对第一和第二电极穿过通孔。

公开(公告)号：US20090308640A1

公开(公告)日：2009-12-17

申请号：US12232253

申请日：2008-09-12

Applicant: Won Kyu Jeung ,  Yi Sung

Inventor： Won Kyu Jeung ,  Yi Sung

IPC: H05K1/03 ,  H05K3/36

CPC classification number: H05K3/4629 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0376 ,  H05K2201/0949 ,  H05K2201/10378 ,  Y10T29/49126 ,  H01L2924/00

Abstract: Provided is a wafer level package including a first substrate that has circuit patterns provided on the top surface thereof and first vias formed therein, the first vias being electrically connected to the circuit patterns; and a second substrate that is bonded to the bottom surface of the first substrate through anodic bonding and has second vias formed therein.

Abstract translation: 提供了一种晶片级封装，其包括具有设置在其顶表面上的电路图案的第一基板和形成在其中的第一通孔，第一通孔电连接到电路图案; 以及第二基板，其通过阳极接合而结合到第一基板的底表面，并且具有形成在其中的第二通孔。

公开(公告)号：US07592702B2

公开(公告)日：2009-09-22

申请号：US11461211

申请日：2006-07-31

Applicant: J. Shelton Lewis ,  Shawn Lloyd ,  Michael Kochanowski ,  John Oldendorf

Inventor： J. Shelton Lewis ,  Shawn Lloyd ,  Michael Kochanowski ,  John Oldendorf

IPC: H01L23/48

CPC classification number: H05K3/3415 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K3/305 ,  H05K3/3447 ,  H05K3/3468 ,  H05K2201/0209 ,  H05K2201/0949 ,  H05K2201/10734 ,  H05K2203/1476 ,  Y02P70/613

Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.

Abstract translation: 本发明提供导热材料，使得从层的一侧传播的较少热量将到达层的另一侧上的连接材料。 相反，一些热量将被导热材料导出并消散。

公开(公告)号：US20090032921A1

公开(公告)日：2009-02-05

申请号：US12181838

申请日：2008-07-29

Applicant: Yuichi Koga

Inventor： Yuichi Koga

IPC: H01L23/495

CPC classification number: H05K1/181 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/0243 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/096 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: According to one embodiment, a printed wiring board structure includes first and second semiconductor packages each including a substrate, and a printed wiring board including first and second component mounting surfaces having a relationship given as front and back surfaces and an inter-chip connection part provided at one portion thereof, the inter-chip connection part being provided with a plurality of arrayed through conductors penetrating through the first and second component mounting surfaces, wherein the substrates of the first and second semiconductor packages are arranged on the printed wiring board in a positional relationship such that the substrates mounted on the component mounting surfaces are partially overlapped via the printed wiring board, the external connection electrodes provided on the substrates are arrayed on the overlapped portion and are conductively connected to the through conductors arrayed in the inter-chip connection part.

Abstract translation: 根据一个实施例，印刷电路板结构包括每个包括基板的第一和第二半导体封装，以及包括具有作为前后表面的关系的第一和第二元件安装表面的印刷布线板和设置有芯片间连接部分 芯片间连接部分的一部分设置有穿过第一和第二部件安装表面的多个阵列贯通导体，其中第一和第二半导体封装的基板以位置布置在印刷电路板上 关系使得安装在部件安装表面上的基板经由印刷电路板部分地重叠，设置在基板上的外部连接电极排列在重叠部分上，并且导体连接到排列在芯片间连接部分中的贯通导体 。

公开(公告)号：US20080099928A1

公开(公告)日：2008-05-01

申请号：US11930210

申请日：2007-10-31

Applicant: Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L23/52

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US20080084678A1

公开(公告)日：2008-04-10

申请号：US11539893

申请日：2006-10-10

Applicant: Gary R. Burhance ,  John C. Barron ,  Jorge L. Garcia ,  David J. Meyer

Inventor： Gary R. Burhance ,  John C. Barron ,  Jorge L. Garcia ,  David J. Meyer

IPC: H05K1/18

CPC classification number: H05K1/186 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0949 ,  H05K2201/10037

Abstract: A printed circuit board and a method for imbedding a battery in the printed circuit board are disclosed. The method includes connecting the battery to a first inner pad and a second inner pad on an inner core layer and forming a first battery contact between a first outer pad and the first inner pad. The method also includes electrically isolating the first battery contact and forming a second battery contact between a second outer pad and the second inner pad.

Abstract translation: 公开了印刷电路板和将电池嵌入印刷电路板中的方法。 该方法包括将电池连接到内芯层上的第一内垫和第二内垫，并在第一外垫和第一内垫之间形成第一电池接触。 该方法还包括电隔离第一电池触点并在第二外垫和第二内垫之间形成第二电池触点。

公开(公告)号：US20080066304A1

公开(公告)日：2008-03-20

申请号：US11902758

申请日：2007-09-25

Applicant: Deepak Pai ,  Ronald Denny

Inventor： Deepak Pai ,  Ronald Denny

IPC: H05K3/34 ,  H05K3/00

CPC classification number: H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

Abstract translation: 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

公开(公告)号：US20080036058A1

公开(公告)日：2008-02-14

申请号：US11533765

申请日：2006-09-20

Applicant: David C. H. Cheng

Inventor： David C. H. Cheng

IPC: H01L23/02

CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/056 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.

Abstract translation: 提供了包括电路板，加强板和至少一个导电通道的封装基板。 加强板的第一表面设置在电路板上以抵抗电路板的翘曲。 加强板具有对应于暴露在其上的电路板的第一接触件的开口。 此外，导电通道的一端位于开口中并电连接到第一触点，导电通道的另一端位于加强板的第二表面上以形成接合焊盘。