公开(公告)号：US06750396B2

公开(公告)日：2004-06-15

申请号：US09737303

申请日：2000-12-15

Applicant: Apurba Roy

Inventor： Apurba Roy

IPC: H05K500

CPC classification number: H01R12/57 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/52 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/1031 ,  H05K2201/10666 ,  H05K2201/10856 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49211 ,  H01L2924/00

Abstract: A low impedance surface-mount connector includes a length of cylindrical rod having an I-shaped cross section. The device permits interconnection by pick-and-place techniques, and the interconnection has advantageous qualities of low resistance, low inductance, mechanical compliance and ease of manufacture. A first circuit device having one or more circuit components is interconnected with a second circuit device by surface mounting such connectors on the first circuit device, providing corresponding solder pads on the second circuit device, and mounting the connectors of the first circuit device onto the pads of the second.

Abstract translation: 低阻表面安装连接器包括具有I形横截面的圆柱形杆的长度。 该器件允许通过拾取和放置技术进行互连，并且互连具有低电阻，低电感，机械符合性和易于制造的优点。 具有一个或多个电路部件的第一电路装置通过将这种连接器表面安装在第一电路装置上而与第二电路装置互连，在第二电路装置上提供相应的焊盘，并将第一电路装置的连接器安装到焊盘 的第二。

公开(公告)号：US20040066589A1

公开(公告)日：2004-04-08

申请号：US10674471

申请日：2003-10-01

Applicant: TDK CORPORATION

Inventor： Masaaki Togashi ,  Taisuki Ahiko

IPC: H02H007/16

CPC classification number: H01G2/065 ,  H05K1/115 ,  H05K1/141 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/0979 ,  H05K2201/09854 ,  H05K2201/10636 ,  H05K2201/10666 ,  Y02P70/611

Abstract: A multilayer capacitor (2) consisting of a capacitor body (1) and an interposer board (20) arranged underneath it, wherein a pair of land patterns are arranged on a front surface of the interposer board (20) for connection with a pair of terminal electrodes of the capacitor body (11) and (12), and a pair of external electrodes are arranged on a back surface of the interposer board (20) for connection with interconnect patterns (34) of a mounting board (33) by solder (35), the pair of land patterns and the pair of external electrodes being arranged on the interposer board (20) so that a direction of a line connecting the pair of land patterns and a direction of a line connecting the pair of external electrodes intersect perpendicularly.

公开(公告)号：US20030214047A1

公开(公告)日：2003-11-20

申请号：US10259482

申请日：2002-09-30

Inventor： Takashi Noguchi

IPC: H01L023/48

CPC classification number: H01L22/32 ,  H01L23/498 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3651 ,  H05K3/225 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/10666 ,  H05K2203/0195 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A method for mounting a semiconductor device, which can decrease the occurrence rate of failures, a method for repairing a semiconductor device, which can easily repair defective solder joints, and a semiconductor device which makes those methods feasible. A substrate 1 has formed therein through-holes 7 lined on the internal walls with a wiring layer 9, and solder balls 6 are fusion-bonded to the substrate 1 in such a manner as to cover the through-holes 7. In the mounting process or in the repair process, heating probes 41 are passed through the through-holes 7 and thrust into the solder balls 6 to thereby melt the solder balls, and the heating probes are pulled out of the solder balls to let the solder balls cool down. In those processes, only the solder balls 6 can be heated, thereby averting adverse effects on the IC chip 3. In the repair process, the solder balls 6 can be restored to an initial condition free of intermetallic compounds.

Abstract translation: 一种可以降低故障发生率的半导体器件的安装方法，可以容易地修复有缺陷的焊点的半导体器件的修复方法以及使这些方法可行的半导体器件。 衬底1上形成有布线层9内衬在内壁上的通孔7，并且焊球6以覆盖通孔7的方式熔合到衬底1上。在安装过程中 或者在维修过程中，加热用探针41穿过通孔7并推入焊球6，从而熔化焊球，并将加热探针从焊球中拉出以使焊球冷却。 在这些处理中，仅可以加热焊球6，从而避免对IC芯片3的不利影响。在修复过程中，焊球6可以恢复到没有金属间化合物的初始条件。

公开(公告)号：US06617528B2

公开(公告)日：2003-09-09

申请号：US09764476

申请日：2001-01-17

Applicant: Gregg J. Armezzani ,  Matthew A. Heller

Inventor： Gregg J. Armezzani ,  Matthew A. Heller

IPC: H05K111

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/363 ,  H05K2201/096 ,  H05K2201/10666 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/0455 ,  H01L2924/00

Abstract: An electronic package which includes first and second circuitized substrates secured together by a solder member which includes a first contact portion for attachment to a printed circuit board and a second contact portion used to bond the two substrates together (e.g., to form a multi-chip module). Semiconductor chips can be positioned on and electrically coupled to the formed solder members.

Abstract translation: 一种电子封装，其包括通过焊料固定在一起的第一和第二电路化基板，该焊接部件包括用于附接到印刷电路板的第一接触部分和用于将两个基板接合在一起的第二接触部分（例如，以形成多芯片 模块）。 半导体芯片可以定位在所形成的焊料部件上并电耦合到所形成的焊接部件上。

公开(公告)号：US20020131255A1

公开(公告)日：2002-09-19

申请号：US10138173

申请日：2002-05-02

Inventor： Apurba Roy

IPC: H01R012/14

CPC classification number: H01R12/57 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/52 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/1031 ,  H05K2201/10666 ,  H05K2201/10856 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49211 ,  H01L2924/00

Abstract: In accordance with the invention, a low impedance surface-mount connector comprises a length of cylindrical rod having an I-shaped cross section. The device permits interconnection by pick-and-place techniques, and the interconnection has advantageous qualities of low resistance, low inductance, mechanical compliance and ease of manufacture. A first circuit device having one or more circuit components is interconnected with a second circuit device by surface mounting such connectors on the first circuit device, providing corresponding solder pads on the second circuit device, and mounting the connectors of the first circuit device onto the pads of the second.

公开(公告)号：US20020088986A1

公开(公告)日：2002-07-11

申请号：US10005960

申请日：2001-12-03

Inventor： Shun Kayama ,  Shunji Amano ,  Motosuke Ohmi ,  Junichi Ohsako ,  Ryota Odake ,  Hiroshi Ozaki

IPC: H05B033/02 ,  H01L021/00

CPC classification number: H05K3/363 ,  H01L27/32 ,  H05K3/305 ,  H05K3/3489 ,  H05K2201/09481 ,  H05K2201/09572 ,  H05K2201/10128 ,  H05K2201/10666 ,  H05K2203/041 ,  H05K2203/107

Abstract: A display device includes an organic electrroluminescence device provided on a first substrate, conductive metallic films provided on the first substrate at such positions as not to overlap with the organic electroluminescence device, a second substrate having a plurality of holes and conductive connection portions which are provided at peripheral portions forming the holes, and solder portions charged in the holes of the second substrate and, by being melted, electrically connecting the conductive metallic films of the first substrate with the conductive connection portions of the second substrate.

Abstract translation: 显示装置包括设置在第一基板上的有机电致发光器件，设置在不与有机电致发光器件重叠的位置处的第一基板上的导电金属膜，具有多个孔的第二基板和设置有导电连接部的导电连接部 在形成孔的周边部分，以及填充在第二基板的孔中的焊料部分，并且通过熔化将第一基板的导电金属膜与第二基板的导电连接部分电连接。

公开(公告)号：US06410860B2

公开(公告)日：2002-06-25

申请号：US08897428

申请日：1997-07-21

Applicant: Koetsu Tamura

Inventor： Koetsu Tamura

IPC: H05K116

CPC classification number: H05K3/363 ,  H01L2224/32225 ,  H05K3/3478 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10666 ,  H05K2201/10681

Abstract: An electronic circuit package assembly of the present invention and implemented by a TAB (Tape Automated Bonding) system includes a sheet formed of thermosetting resin. The sheet intervenes between a substrate and an organic insulating film carrying an LSI (Large Scale Integrated circuit) chip thereon. Solder is buried in the sheet beforehand. The assembly is heated to cause the solder to melt and connect wiring electrodes formed on the substrate and outer leads provided on the organic insulating film. The assembly has high reliability when compared with other connection methods using solder and effectively prevents migration of the tape carrier.

Abstract translation: 本发明的电子电路封装组件由TAB（Tape Automated Bonding）系统实现，包括由热固性树脂形成的片材。 片材介于衬底和承载LSI（大规模集成电路）芯片的有机绝缘膜之间。 事先将焊料埋在片材中。 加热组件使焊料熔化并连接形成在基板上的布线电极和设置在有机绝缘膜上的外引线。 与使用焊料的其他连接方法相比，该组件具有高可靠性，并且有效地防止了带状载体的迁移。

公开(公告)号：US06316737B1

公开(公告)日：2001-11-13

申请号：US09393952

申请日：1999-09-09

Applicant: Michael D. Evans ,  James D. Goss ,  Jeffrey A. Curhan ,  Patrizio Vinciarelli

Inventor： Michael D. Evans ,  James D. Goss ,  Jeffrey A. Curhan ,  Patrizio Vinciarelli

IPC: H05K116

CPC classification number: H05K1/111 ,  H01L2224/48091 ,  H01L2924/01079 ,  H05K1/0306 ,  H05K1/182 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0179 ,  H05K2201/09572 ,  H05K2201/09745 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2203/0455 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

Abstract: In general, in one aspect, the invention features a connection between a through-hole in a circuit board and a contact region on a component. The contact region has a surface bearing a depression. A continuous solder column has one end of that forms a solder joint with an inner wall of the through-hole and the other end of that forms a solder joint with the contact region.

Abstract translation: 通常，一方面，本发明的特征在于电路板中的通孔与部件上的接触区域之间的连接。 接触区域具有带凹陷的表面。 连续的焊料柱的一端与通孔的内壁形成焊接点，另一端与接触区域形成焊接点。

公开(公告)号：US06281040B1

公开(公告)日：2001-08-28

申请号：US09397614

申请日：1999-09-16

Applicant: Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

Inventor： Mark Thomas McCormack ,  Hunt Hang Jiang ,  Solomon I. Beilin ,  Albert Wong Chan ,  Yasuhito Takahashi

IPC: H01L2144

CPC classification number: H05K3/363 ,  H01L23/49883 ,  H01L2224/16503 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10666 ,  H05K2203/0425 ,  H05K2203/0455

Abstract: Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.

Abstract translation: 公开了制造电路基板和电气组件的方法。 导电组合物设置在相对的导电区域之间，并且可以被固化以形成通孔结构。 导电组合物包括导电颗粒和载体。 载体可以包括助熔剂和在25℃下粘度小于约1000厘泊的环氧官能树脂。

公开(公告)号：US06183588B2

公开(公告)日：2001-02-06

申请号：US09460488

申请日：1999-12-14

Applicant: Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

Inventor： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B3100

CPC classification number: B32B43/00 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K3/007 ,  H05K3/025 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/467 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Abstract translation: 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。