公开(公告)号：US07271347B2

公开(公告)日：2007-09-18

申请号：US11305120

申请日：2005-12-19

Applicant: Yasuhito Ohwaki

Inventor： Yasuhito Ohwaki

IPC: H05K1/16

CPC classification number: H05K1/111 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/108 ,  H05K3/423 ,  H05K2201/09554 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wired circuit board is provided having excellent heat radiation characteristics, including when the semiconductor device is mounted on the wired circuit board by the flip chip mounting method. An insulating base layer defines a base opening portion in a mounting region. The base opening portion includes a thin layer portion that surrounds the base opening portion. Inside terminal portions are disposed on the thin layer portion. A heat radiating portion is formed in the base opening region to contact the stiffener sheet As a result, the surface of the inside terminal portion is located lower in level than the surface of the heat radiating portion. Thus, a semiconductor device may be mounted on the wired circuit board by the flip chip mounting method to enable heat generated from the semiconductor device to be transferred to the stiffener sheet via the heat radiating portion.

Abstract translation: 提供了具有优异的散热特性的布线电路板，包括当通过倒装芯片安装方法将半导体器件安装在布线电路板上时。 绝缘基层在安装区域中限定基部开口部分。 基部开口部包括围绕基部开口部的薄层部。 内部端子部分设置在薄层部分上。 在基部开口区域中形成有热辐射部分以接触加强片。因此，内部端子部分的表面位于比散热部分的表面更低的水平面上。 因此，半导体器件可以通过倒装芯片安装方法安装在布线电路板上，以使得从半导体器件产生的热能够经由散热部分传递到加强板。

公开(公告)号：US07185426B1

公开(公告)日：2007-03-06

申请号：US10806640

申请日：2004-03-23

Applicant: David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

Inventor： David Jon Hiner ,  Ronald Patrick Huemoeller ,  Sukianto Rusli

IPC: H05K3/30

CPC classification number: H01L24/73 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1815 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/423 ,  H05K7/1061 ,  H05K2201/09036 ,  H05K2201/09554 ,  H05K2203/0723 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.

Abstract translation: 包括用于安装另一半导体封装的顶表面端子的半导体封装提供三维电路配置，其可以提供具有标准设计的现有格栅阵列封装的可移除连接。 半导体管芯安装在电连接到具有设置在底侧的端子的电路基板上，用于连接到外部系统。 封装裸片和衬底，并且将通孔激光烧蚀或以其它形式通过封装形成到衬底的顶表面上的端子，其提供可安装另一个栅格阵列半导体封装的栅格阵列安装焊盘。 通孔的底侧可以终止并电连接到基板上的端子，半导体封装的底部的端子（通过端子）或半导体管芯的顶部上的端子。 通孔可以被电镀，糊状填充，填充低熔点合金，并且可以具有锥形轮廓以改善电镀性能。

公开(公告)号：US07152315B1

公开(公告)日：2006-12-26

申请号：US10826019

申请日：2004-04-17

Applicant: Mohan R. Paruchuri

Inventor： Mohan R. Paruchuri

IPC: H05K3/20

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K3/445 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A method 10, 80, 81 for making multi-layer electronic circuit boards 77, 137, 139 having metallized apertures 18, 20, 34, 40, 104, 106, 120.

Abstract translation: 一种用于制造具有金属化孔18,20,34,40,104,106,120的多层电子电路板77,137,139的方法10,80,81。

公开(公告)号：US07132607B2

公开(公告)日：2006-11-07

申请号：US10860491

申请日：2004-06-04

Applicant: Takeshi Yoshimi ,  Tetsuya Osawa

Inventor： Takeshi Yoshimi ,  Tetsuya Osawa

IPC: H05K1/03

CPC classification number: H05K1/0218 ,  H05K1/056 ,  H05K3/4644 ,  H05K2201/09554

Abstract: A wired circuit board is provided having enhanced reliability of electrical connection between a metal substrate and a shield layer to achieve significant noise reduction reliably. An insulating base layer is formed on the metal substrate, while resin layers are formed on the metal substrate with a predetermined space provided from the both widthwise sides of the insulating base layer. A conductor layer is formed having a predetermined wired circuit pattern on the insulating base layer. Thereafter, an insulating cover layer is formed on the insulating base layer in such a manner as to cover the conductor layer. Then, a shield layer is laminated on the metal substrate to cover the insulating cover layer and also is put in close contact with the resin layers at end portions thereof by a vacuum film-forming method or by plating.

Abstract translation: 提供了一种布线电路板，其具有在金属基板和屏蔽层之间具有增强的电连接的可靠性，以可靠地实现显着的降噪。 在金属基板上形成绝缘基层，同时在金属基板上形成有从基底绝缘层的宽度方向两侧设置的预定空间的树脂层。 在绝缘基底层上形成具有预定布线电路图案的导体层。 此后，以覆盖导体层的方式在绝缘基底层上形成绝缘覆盖层。 然后，在金属基板上层压屏蔽层以覆盖绝缘覆盖层，并且还通过真空成膜方法或通过电镀在其端部与树脂层紧密接触。

公开(公告)号：US07121840B1

公开(公告)日：2006-10-17

申请号：US11395400

申请日：2006-03-30

Applicant: Warren Coon

Inventor： Warren Coon

IPC: H01R12/00

CPC classification number: G11B15/689 ,  H01R4/06 ,  H01R12/526 ,  H05K1/056 ,  H05K3/4046 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A resin free and solder free electrical connection in a disk drive suspension interconnect is provided including an electrical connection between conductive traces of a first metal layer and a second metal layer with a conductor pin having electrical connection with the outer surfaces of each metal layer and free of any solder and resin in making the connection.

Abstract translation: 提供了一种在盘驱动器悬挂互连中的无树脂和无焊料的电连接，其包括在第一金属层的导电迹线和第二金属层之间的电连接，导体引脚与每个金属层的外表面电连接， 任何焊料和树脂进行连接。

公开(公告)号：US20060131065A1

公开(公告)日：2006-06-22

申请号：US11305120

申请日：2005-12-19

Applicant: Yasuhito Ohwaki

Inventor： Yasuhito Ohwaki

IPC: H05K7/20 ,  H01L23/34

CPC classification number: H05K1/111 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/108 ,  H05K3/423 ,  H05K2201/09554 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wired circuit board that can produce excellent heat radiation characteristics even when the semiconductor device is mounted on the wired circuit board by the flip chip mounting method. The base opening portion 8 and the thin layer portion 9 to surround the base opening portion 8 are formed in a portion of the insulating base layer 3 corresponding to the mounting portion 7. Also, the inside terminal portions 15 of the terminal portions 13 are disposed on the thin layer portions 9 and the heat radiating portions 17 contacting with the stiffener sheet 2 are formed in the base opening portion 8. As a result of this, the surface of the inside terminal portion 15 is located lower in level than the surface of the heat radiating portion 17. This can allow the semiconductor device S mounted via the bumps 25 and the heat radiating portion 17 to be located close to each other. This can provide the result that the semiconductor device S can be reliably mounted on the wired circuit board 1 by the flip chip mounting method, while also the heat generated from the semiconductor device S can be transferred to the stiffener sheet 2 effectively via the heat radiating portion 17. This can provide improved heat radiating ability of the wired circuit board.

Abstract translation: 即使半导体器件通过倒装芯片安装方法安装在布线电路板上也能产生优异的散热特性的布线电路板。 在与安装部7对应的绝缘基底层3的一部分上形成有基部开口部8和围绕基部开口部8的薄层部9.另外，端子部13的内部端子部15 在基部开口部8上形成有薄壁部9和与加强板2接触的散热部17。结果，内部端子部15的表面位于比下侧 散热部17.这可以使经由凸块25和散热部17安装的半导体装置S彼此靠近。 这可以提供通过倒装芯片安装方法将半导体器件S可靠地安装在布线电路板1上的结果，同时半导体器件S产生的热也可以通过散热有效地传递到加强片2 这可以提供有线电路板的改善的散热能力。

公开(公告)号：US20060040522A1

公开(公告)日：2006-02-23

申请号：US11211810

申请日：2005-08-25

Applicant: Thomas Distefano ,  Joseph Fjelstad

Inventor： Thomas Distefano ,  Joseph Fjelstad

IPC: H05K1/00

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

Abstract: A microelectronic interposer is made by providing a sacrificial layer over the surface of a planar body. Apertures are formed passing through the body and the sacrificial layer. A layer of an electrically conductive structural material is deposited in each of the apertures and over the sacrificial layer, proximate to each aperture to thereby form contacts. The sacrificial layer is removed leaving the contacts with outwardly flaring peripheral portions spaced vertically above the surface of the planar body.

Abstract translation: 通过在平面体的表面上设置牺牲层来制造微电子插入器。 形成穿过身体和牺牲层的孔。 一层导电结构材料沉积在每个孔中并在牺牲层上方，靠近每个孔，从而形成接触。 去除牺牲层，留下接触件，其外部扩张的外围部分在平面体的表面上方垂直地间隔开。

公开(公告)号：US20050282088A1

公开(公告)日：2005-12-22

申请号：US11156607

申请日：2005-06-21

Applicant: Hidenori Aonuma ,  Yasuhito Ohwaki

Inventor： Hidenori Aonuma ,  Yasuhito Ohwaki

IPC: G03C5/00 ,  H05K1/03 ,  H05K1/05 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/44

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/06 ,  H05K3/108 ,  H05K3/243 ,  H05K2201/09554 ,  H05K2201/0969 ,  H05K2203/0323 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A production method of a suspension board with circuit that can provide reduced number of man-hour and complicated processes for forming the ground terminal, to provide production cost reduction. An insulating base layer 4 having a base opening portion 3 is formed on a metal board 2 at a ground terminal 13 forming position, and a thin metal film 5 is formed on the metal board 2 exposed in the base opening portion 3 and on the insulating base layer 4. Then, a conductive pattern 7 is formed on the thin metal film 5. Then, an insulating cover layer 9 covering the conductive pattern 7 and having a cover opening portion 8 which correspond in position to the base opening portion 3 is formed on the insulating base layer 4. Then, a metal board opening portion 11 from which the base opening portion 3 and the insulating base layer 4 around it are exposed is formed in the metal board 2. Then, an electrolytic plating layer 12 is formed on each side of the conductive pattern 7 exposed in the cover opening portion 8, feeding electric power from the conductive pattern 7, and a metal filling layer 14 is formed in the metal board opening portion 11, to allow the electrolytic plating layer 12 and the metal board 2 to be conductive with each other.

Abstract translation: 一种具有电路的悬挂板的制造方法，其能够提供减少的工时数量和复杂的用于形成接地端子的工艺，以提供生产成本降低。 在接地端子13的形成位置的金属板2上形成具有基部开口部3的绝缘基底层4，在露出于基部开口部3的绝缘金属板2上形成金属薄膜5， 基层4。 然后，在金属薄膜5上形成导电图案7。 然后，在基底绝缘层4上形成覆盖导电图案7并且具有与基部开口部3相对应的盖开口部8的绝缘覆盖层9。 然后，在金属板2上形成金属基板开口部11，基部开口部3及其周围的绝缘基底层4露出。 然后，在暴露于盖开口部8的导电图案7的两侧形成电解镀层12，从导电图案7供给电力，在金属板开口部11形成有金属填充层14， 以使电解镀层12和金属板2彼此导电。

公开(公告)号：US06954987B2

公开(公告)日：2005-10-18

申请号：US10849478

申请日：2004-05-19

Applicant: Kenneth Daryl Wong ,  Sean L. Bell

Inventor： Kenneth Daryl Wong ,  Sean L. Bell

IPC: H05K3/00 ,  H05K3/34 ,  H05K3/44 ,  H01K3/10

CPC classification number: H05K3/44 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09063 ,  H05K2201/09554 ,  H05K2201/10666 ,  H05K2203/1178 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board assembly employing a solder vent hole adjacent solder filled interconnect vias connecting to a conductive pallet, is disclosed. The solder vent hole allows gases to escape from an otherwise sealed cavity during solder reflow, relieving positive pressure and thereby allowing solder to flow into it. By providing an escape path for trapped air and gases generated during solder paste reflow, the out-gassing pressure and weight of the molten solder is sufficient to allow the solder paste to flow into the cavity.

Abstract translation: 公开了一种印刷电路板组件，其采用与连接到导电托盘的焊料填充的互连通孔相邻的焊剂通气孔。 焊锡通气孔允许气体在回流焊接过程中从另一个密封的空腔中逸出，减轻正压，从而允许焊料流入其中。 通过为焊膏回流期间产生的被捕获的空气和气体提供逃生路径，熔融焊料的排气压力和重量足以使焊膏流入空腔。

公开(公告)号：US20050224961A1

公开(公告)日：2005-10-13

申请号：US11148890

申请日：2005-06-08

Applicant: Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

Inventor： Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

IPC: H01L21/48 ,  H01L23/34 ,  H01L23/373 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/068 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract translation: 电子封装和形成方法。 提供具有第一和第二相对表面的导热层。 第一电介质层在加压下被层压在导热层的第一相对表面上，温度在最低温度T 1 1MIN和最高温度T 1MAX之间。 在层压之后，T 1MAX 3将第一介电层的延展性约束至少为D 1。 T 1MAX取决于D 1和在由第一介电层组成的第一电介质材料上。 在加压下将第二电介质层在导热层的第二相对表面上，在最低温度T 2 M 2 N 2和最大温度T 2 MAX之间的温度下层压。 在层压之后，T 2MAX 2将第二介电层的延展性约束为至少D 2。 T 2MAX取决于D 2和在由第二介电层组成的第二电介质材料上。