公开(公告)号：US09735225B2

公开(公告)日：2017-08-15

申请号：US14956939

申请日：2015-12-02

Applicant: ROHM CO., LTD.

Inventor： Hiroshi Tamagawa ,  Yasuhiro Kondo ,  Yasuhiro Fuwa ,  Hiroyuki Okada ,  Eiji Nukaga ,  Katsuya Matsuura

IPC: H01C10/00 ,  H01L49/02 ,  H01L27/08 ,  H01L27/06 ,  H01L21/308 ,  H01C1/14 ,  H01C13/02 ,  H01L21/3065 ,  H01C17/242 ,  H01C17/00 ,  H05K3/34

CPC classification number: H01L28/20 ,  H01C1/14 ,  H01C13/02 ,  H01C17/006 ,  H01C17/242 ,  H01L21/3065 ,  H01L21/3083 ,  H01L27/0676 ,  H01L27/0802 ,  H05K3/3431 ,  H05K2201/10674

Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.

公开(公告)号：US09721881B1

公开(公告)日：2017-08-01

申请号：US15142644

申请日：2016-04-29

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Zhiwei Gong ,  Wei Gao

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/09 ,  H01L25/162 ,  H01L2224/04042 ,  H01L2224/48091 ,  H05K1/115 ,  H05K1/141 ,  H05K1/181 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613

Abstract: A method of forming a semiconductor device assembly includes forming an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The method further includes attaching the first major surface of the interposer to a packaged semiconductor device, wherein the opening of the interposer exposes the packaged semiconductor device.

公开(公告)号：US09706663B2

公开(公告)日：2017-07-11

申请号：US14840693

申请日：2015-08-31

Applicant: IBIDEN CO., LTD.

Inventor： Hajime Sakamoto ,  Masatoshi Kunieda ,  Makoto Terui ,  Takashi Kariya

IPC: H01L23/538 ,  H05K1/18 ,  H05K1/14

CPC classification number: H05K1/181 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/141 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.

公开(公告)号：US20170194552A1

公开(公告)日：2017-07-06

申请号：US15379521

申请日：2016-12-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiharu SUEMORI

IPC: H01L41/053 ,  H01L41/047

CPC classification number: H01L41/0533 ,  H01L23/3121 ,  H01L23/564 ,  H01L25/16 ,  H01L41/0472 ,  H01L41/0475 ,  H01L41/0477 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H03H9/1085 ,  H05K3/281 ,  H05K3/284 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3494 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10068 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/1178 ,  H05K2203/1311 ,  H05K2203/1316 ,  H05K2203/1322 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/014

Abstract: An electronic component-containing module includes a board, electronic components, and a sealing resin and includes a space provided between the board and at least one of the electronic components. The dryness factor of the sealing resin is about 60% or more where, after the electronic component-containing module is moisturized, the electronic component-containing module is heated to the re-melting temperature of a brazing filler metal.

公开(公告)号：US09691724B2

公开(公告)日：2017-06-27

申请号：US14161735

申请日：2014-01-23

Applicant: GE Embedded Electronics Oy

Inventor： Antti Iihola ,  Risto Tuominen

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H05K1/18 ,  H01L25/065 ,  H05K3/30

CPC classification number: H01L24/09 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0969 ,  H05K2201/10674 ,  H01L2924/00

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

公开(公告)号：US09691699B2

公开(公告)日：2017-06-27

申请号：US14931808

申请日：2015-11-03

Applicant: Unimicron Technology Corp.

Inventor： Chia-Chan Chang ,  Gwo-Chaur Chen ,  Yung-Tsai Chen

IPC: H05K3/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/09 ,  H01L21/4846 ,  H01L21/4875 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/1531 ,  H01L2924/3511 ,  H05K1/181 ,  H05K3/007 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers.

公开(公告)号：US09674940B2

公开(公告)日：2017-06-06

申请号：US14826207

申请日：2015-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eung-chang Lee ,  Seok-jae Han

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC classification number: H05K1/0206 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/00 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83224 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/181 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/09345 ,  H05K2201/096 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2201/10969 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00

Abstract: An electronic device and semiconductor package include a printed circuit board and a semiconductor device mounted thereon. The printed circuit board includes one or more thermally conductive vias for dissipating heat.

公开(公告)号：US09664964B2

公开(公告)日：2017-05-30

申请号：US14678406

申请日：2015-04-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chong-Guk Lee ,  Joo-Yeon Won ,  Se-Hui Jang ,  Su-Mi Moon ,  Dong-Wook Lee

IPC: H01L23/48 ,  G02F1/1345 ,  H01L27/12 ,  H01L23/498 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC Chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

公开(公告)号：US20170148771A1

公开(公告)日：2017-05-25

申请号：US15226209

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Goo CHA ,  Yong II KIM ,  Wan tae LIM

IPC: H01L25/075 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L33/20 ,  H01L33/38 ,  H01L33/505 ,  H01L33/62 ,  H05K1/00 ,  H05K1/181 ,  H05K1/183 ,  H05K3/301 ,  H05K3/325 ,  H05K2201/083 ,  H05K2201/0939 ,  H05K2201/09472 ,  H05K2201/10106 ,  H05K2201/10674 ,  H05K2201/209 ,  H05K2203/104 ,  H05K2203/168 ,  Y02P70/611

Abstract: A light source module includes a circuit board having a plurality of chip mounting regions, the plurality of chip mounting regions respectively having at least one connection pad; at least one alignment component respectively disposed on the plurality of chip mounting regions, and having a convex or concave shape; and a plurality of LED chips respectively mounted on the plurality of chip mounting regions, respectively having at least one electrode electrically connected to the at least one connection pad, and respectively coupled to the at least one alignment component.

公开(公告)号：US09645163B2

公开(公告)日：2017-05-09

申请号：US14240503

申请日：2012-08-24

Applicant: Thomas Fischer ,  Stefan Günthner ,  Dietmar Huber ,  Jakob Schillinger

Inventor： Thomas Fischer ,  Stefan Günthner ,  Dietmar Huber ,  Jakob Schillinger

IPC: G01P15/08 ,  G01P1/02 ,  B81C1/00

CPC classification number: G01P1/023 ,  B81C1/0023 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/13101 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/10924 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A sensor having at least one sensor element (1), at least one signal processing element (2), and a housing (7) which has at least one fastening means. An electrical interface is provided for electrically connecting the sensor. The sensor has an electrically and mechanically connecting carrier means (4) on which the at least one sensor element (1) and the signal processing element (2) are arranged and are electrically connected to the carrier means. The carrier means (4) is also at least electrically connected to the electrical interface.