公开(公告)号：US20170158493A1

公开(公告)日：2017-06-08

申请号：US15440962

申请日：2017-02-23

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81B7/00 ,  B81C1/00 ,  B01D67/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.

公开(公告)号：US09656860B2

公开(公告)日：2017-05-23

申请号：US15254828

申请日：2016-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Earl Vedere Atnip ,  Raul Enrique Barreto ,  Kelly J. Taylor

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00365 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0167 ,  B81C2201/0178

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

公开(公告)号：US20170129767A1

公开(公告)日：2017-05-11

申请号：US15411957

申请日：2017-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Tsai-Hao HUNG ,  Shih-Chi KUO ,  Tsung-Hsien LEE ,  Tao-Cheng LIU

IPC: B81B1/00 ,  B81C1/00

CPC classification number: B81B1/004 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0163 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/012 ,  B81C1/00087 ,  B81C1/00619 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2203/0118

Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

公开(公告)号：US09618342B2

公开(公告)日：2017-04-11

申请号：US14270596

申请日：2014-05-06

Applicant: Chinese Academy of Sciences Institute of Geology and Geophysics

Inventor： Lian Zhong Yu ,  Chen Sun

IPC: G01C19/5747 ,  G01C19/5769

CPC classification number: G01C19/5769 ,  B81B3/0048 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81B2203/0136 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0176 ,  B81C2203/0118 ,  G01C19/574 ,  G01C19/5747

Abstract: A MEMS anti-phase vibratory gyroscope includes two measurement masses with a top cap and a bottom cap each coupled with a respective measurement mass. The measurement masses are oppositely coupled with each other in the vertical direction. Each measurement mass includes an outer frame, an inner frame located within the outer frame, and a mass located within the inner frame. The two measurement masses are coupled with each other through the outer frame. The inner frame is coupled with the outer frame by a plurality of first elastic beams. The mass is coupled with the inner frame by a plurality of second elastic beams. A comb coupling structure is provided along opposite sides of the outer frame and the inner frame. The two masses vibrate toward the opposite direction, and the comb coupling structure measures the angular velocity of rotation.

公开(公告)号：US09610543B2

公开(公告)日：2017-04-04

申请号：US14170187

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: H01L21/00 ,  B01D67/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

公开(公告)号：US20170081176A1

公开(公告)日：2017-03-23

申请号：US14981461

申请日：2015-12-28

Applicant: HANGZHOU SILAN MICROELECTRONICS CO., LTD. ,  HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD

Inventor： Feng JI ,  Yongxiang WEN ,  Chen LIU ,  Hao ZHOU

IPC: B81B7/00 ,  H01L23/26 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2203/0315 ,  B81B2203/033 ,  B81B2203/0384 ,  B81C1/00285 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0154 ,  B81C2201/0198 ,  B81C2203/0109 ,  H01L23/26

Abstract: The invention provides a MEMS device, semiconductor device, and method for manufacturing the same. The MEMS device comprises an enclosed cavity, the cavity having an inner wall extending in a first plane, the inner wall including a film deposition region for depositing a getter film, wherein one or more grooves are formed in the film deposition region, the angle between the sidewalls of the grooves and the first plane is more than 0° and less than 180°, and the getter film overlays the sidewall of the grooves. The invention can form the getter film in a smaller incident flux angle with a common sputtering, evaporation apparatus, that is, form the porous, high roughness getter.

公开(公告)号：US20170044006A1

公开(公告)日：2017-02-16

申请号：US15305799

申请日：2014-11-05

Applicant: ADVANCED SEMICONDUCTOR MANUFACTURING CO. LTD

Inventor： Yuanjun Xu ,  Yilin Yan ,  Weijia Xue

IPC: B81B7/02 ,  B81C1/00

CPC classification number: B81B7/02 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/019 ,  B81C2201/0198 ,  B81C2201/053

Abstract: There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

Abstract translation: 提供了使用该方法形成复合腔和复合腔的方法。 该方法包括以下步骤：提供硅衬底（101）; 在其前侧形成氧化物层; 图案化氧化物层以形成一个或多个凹槽（103），凹槽（103）的位置对应于待形成的小空腔（109）的位置; 提供接合晶片（104），其接合到所述图案化氧化物层以在所述硅衬底（101）和所述接合晶片（104）之间形成一个或多个闭合微腔结构（105）; 在所述接合晶片（104）上形成保护膜（106），并在所述硅衬底（101）的背侧上形成掩模层（107）; 图案化掩模层（107），对应于待形成的大空腔（108）的位置的掩模层（107）的图案; 使用掩模层（107）作为掩模，从背面蚀刻硅衬底（101）直到其前侧的氧化物层在硅衬底（101）中形成大空腔（108）; 并且使用所述掩模层（107）和所述氧化物层作为掩模，通过所述硅衬底（101）从所述背面蚀刻所述接合晶片（104）直到所述保护膜（106）在其上形成一个或多个小空腔 109）。 复合空腔中的小空腔（109）所在的半导体介质层的厚度均匀性由本发明很好地控制。

公开(公告)号：US20170043501A1

公开(公告)日：2017-02-16

申请号：US15306477

申请日：2015-04-22

Applicant: Master Dynamic Limited

Inventor： Yingnan WANG ,  Jianxing HUANG

IPC: B28D5/04 ,  C09K13/08 ,  G03F7/40

CPC classification number: B28D5/04 ,  B81C1/00626 ,  B81C2201/0132 ,  C09K13/08 ,  G03F7/405

Abstract: A method of forming a multi-level component includes the step of forming at least one arrangement of micro trenches in a predetermined arrangement in a mask material by a lithography process. Another step involves applying one or more etching processes to a surface of a component upon which the mask is applied. The micro trenches have either first or second different aspect ratios. In the applying step, the component is etched by an aspect ratio dependent etch (ARDE) process so as to form an arrangement of micro trenches and micro pillars between adjacent micro trenches. Another step involves removing the arrangement of micro pillars from the component by a removal process. There is also a multi-level component made according to the above method with a first portion at a first level and a further portion of a further level different from the first level.

Abstract translation: 形成多级部件的方法包括通过光刻工艺在掩模材料中以预定布置形成至少一个微沟槽布置的步骤。 另一步骤包括对施加掩模的部件的表面施加一个或多个蚀刻工艺。 微沟槽具有第一或第二不同的纵横比。 在施加步骤中，通过纵横比依赖蚀刻（ARDE）工艺来蚀刻部件，以便在相邻的微沟槽之间形成微沟槽和微柱的布置。 另一个步骤是通过移除过程从组件中移除微柱的排列。 还有根据上述方法制造的多级组件，其中第一部分处于第一级，而另一部分又与第一级不同。

公开(公告)号：US20160378064A1

公开(公告)日：2016-12-29

申请号：US15171012

申请日：2016-06-02

Applicant: Nivarox-FAR S.A.

Inventor： Alex GANDELHMAN

IPC: G04D99/00 ,  C23F1/00

CPC classification number: G04D99/00 ,  B81B2201/035 ,  B81B2203/0384 ,  B81C1/00103 ,  B81C2201/0132 ,  B81C2201/0138 ,  B81C2201/014 ,  C23F1/00

Abstract: The invention relates to a silicon-based component with at least one chamfer formed from a method combining at least one oblique side wall etching step with a “Bosch” etching of vertical side walls, thereby enabling aesthetic improvement and improvement in the mechanical strength of components formed by micromachining a silicon-based wafer.

Abstract translation: 本发明涉及一种具有至少一个倒角的硅基组件，该方法将至少一个倾斜侧壁蚀刻步骤与垂直侧壁的“博世”蚀刻相结合，从而使得美观改进和组件的机械强度得到改善 通过微加工硅基晶片形成。

公开(公告)号：US20160368765A1

公开(公告)日：2016-12-22

申请号：US15254828

申请日：2016-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Earl Vedere Atnip ,  Raul Enrique Barreto ,  Kelly J. Taylor

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00365 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0167 ,  B81C2201/0178

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract translation: 在所描述的示例中，通过在衬底上形成牺牲层并在牺牲层上形成第一金属层来形成MEMS器件。 随后，将第一金属层暴露于氧化环境中，氧化暴露于氧化环境的第一金属层的表面层，以形成第一金属层的天然氧化物层。 随后在第一金属层的自然氧化物层上形成第二金属层。 随后去除牺牲层，形成释放的金属结构。