公开(公告)号：US20160362788A1

公开(公告)日：2016-12-15

申请号：US15107878

申请日：2015-01-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Shinichi KURITA ,  Jozef KUDELA ,  John M. WHITE ,  Dieter HAAS

IPC: C23C16/455 ,  H01L51/52 ,  H01L51/56

CPC classification number: C23C16/45548 ,  C23C16/042 ,  C23C16/4402 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32467 ,  H01J37/32513 ,  H01J37/32715 ,  H01J37/32834 ,  H01J37/32853 ,  H01J37/32899 ,  H01J2237/327 ,  H01J2237/3321 ,  H01L21/6719 ,  H01L21/67748 ,  H01L21/67751 ,  H01L21/68742 ,  H01L51/0011 ,  H01L51/5237 ,  H01L51/5253 ,  H01L51/56

Abstract: The present disclosure relates to methods and apparatus for an atomic layer deposition (ALD) processing chamber for device fabrication and methods for replacing a gas distribution plate and mask of the same. The ALD processing chamber has a slit valve configured to allow removal and replacement of a gas distribution plate and mask. The ALD processing chamber may also have actuators operable to move the gas distribution plate to and from a process position and a substrate support assembly operable to move the mask to and from a process position.

Abstract translation: 本公开涉及用于器件制造的原子层沉积（ALD）处理室的方法和装置以及用于替换气体分布板及其掩模的方法。 ALD处理室具有狭缝阀，其构造成允许气体分配板和掩模的移除和更换。 ALD处理室还可以具有可操作以将气体分配板移动到过程位置和从处理位置移动的致动器和可操作以将掩模移动到过程位置和从处理位置移动掩模的基板支撑组件。

公开(公告)号：US20160358794A1

公开(公告)日：2016-12-08

申请号：US15158788

申请日：2016-05-19

Applicant: Tokyo Electron Limited

Inventor： Shigehiro MIURA

IPC: H01L21/67 ,  H01L21/311 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01J37/3244 ,  C23C16/402 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/56 ,  H01J37/32366 ,  H01J37/32715 ,  H01J37/32724 ,  H01J37/32733 ,  H01J37/32816 ,  H01J37/32899 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/68764 ,  H01L21/68771

Abstract: A substrate processing apparatus includes a vacuum chamber and a turntable provided in the vacuum chamber. The turntable includes a substrate receiving area formed in a surface along a circumferential direction thereof. An etching area is provided at a predetermined area along the circumferential direction of the turntable. An etching gas supply unit is provided in the etching area so as to face the surface of the turntable and including gas discharge holes arranged extending in a radial direction of the turntable. A reaction energy decrease prevention unit configured to prevent a decrease in etching reaction energy in an outer area of the turntable in the etching area is provided.

Abstract translation: 基板处理装置包括真空室和设置在真空室中的转盘。 转盘包括沿其圆周方向形成在表面中的基板接收区域。 沿着转台的圆周方向的预定区域设置蚀刻区域。 蚀刻气体供给单元设置在蚀刻区域中，以面对转台的表面，并且包括沿着转盘的径向方向延伸的排气孔。 提供了一种反应能量减少预防单元，其被配置为防止在蚀刻区域中的转台的外部区域中的蚀刻反应能量的降低。

公开(公告)号：US20160343580A1

公开(公告)日：2016-11-24

申请号：US15225489

申请日：2016-08-01

Applicant: Lam Research Corporation

Inventor： Eric A. Hudson

IPC: H01L21/311 ,  H01J37/32 ,  H01L21/67 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L21/31116 ,  C23C16/45525 ,  C23C16/45544 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32513 ,  H01J37/32577 ,  H01J37/32623 ,  H01J37/32651 ,  H01J37/32871 ,  H01J37/32899 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/30655 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/67069 ,  H01L27/1087 ,  H01L27/11556 ,  H01L27/11582

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.

公开(公告)号：US20160268110A1

公开(公告)日：2016-09-15

申请号：US15138154

申请日：2016-04-25

Applicant: INTEVAC, INC.

Inventor： David Ward Brown ,  Vinay Shah ,  Terry Pederson ,  Terry Bluck

IPC: H01J37/34 ,  C23C14/56 ,  H01J37/32 ,  C23C14/35

CPC classification number: H01J37/3455 ,  C23C14/35 ,  C23C14/56 ,  H01J37/32779 ,  H01J37/32899 ,  H01J37/3405 ,  H01J37/3417 ,  H01J37/3452

Abstract: A sputtering system having a processing chamber with an inlet port and an outlet port, and a sputtering target positioned on a wall of the processing chamber. A movable magnet arrangement is positioned behind the sputtering target and reciprocally slides behinds the target. A conveyor continuously transports substrates at a constant speed past the sputtering target, such that at any given time, several substrates face the target between the leading edge and the trailing edge. The movable magnet arrangement slides at a speed that is at least several times faster than the constant speed of the conveyor. A rotating zone is defined behind the leading edge and trailing edge of the target, wherein the magnet arrangement decelerates when it enters the rotating zone and accelerates as it reverses direction of sliding within the rotating zone.

公开(公告)号：US20160268107A1

公开(公告)日：2016-09-15

申请号：US14656588

申请日：2015-03-12

Applicant: ASM IP Holding B.V.

Inventor： Carl Louis White ,  Mohith Verghese ,  Eric James Shero ,  Todd Robert Dunn

IPC: H01J37/32

CPC classification number: H01J37/32899 ,  H01J37/3244 ,  H01J37/32513 ,  H01J37/32715 ,  H01J37/32733

Abstract: Multi-zone reactors, systems including a multi-zone reactor, and methods of using the systems and reactors are disclosed. Exemplary multi-zone reactors include a movable susceptor assembly and a moveable plate. The movable susceptor assembly and movable plate can move vertically between reaction zones of a reactor to expose a substrate to multiple processes or reactants.

Abstract translation: 公开了多区域反应器，包括多区域反应器的系统以及使用该系统和反应器的方法。 示例性多区域反应器包括可移动基座组件和可移动板。 活动基座组件和可移动板可以在反应器的反应区之间垂直移动以将基底暴露于多个过程或反应物。

公开(公告)号：US20160260620A1

公开(公告)日：2016-09-08

申请号：US15157303

申请日：2016-05-17

Applicant: Lam Research Corporation

Inventor： Joseph Scott Briggs ,  Eric A. Hudson

IPC: H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  C23C16/52 ,  H01J37/32 ,  C23C16/50 ,  C23C16/455 ,  H01L21/3065 ,  H01L27/115

CPC classification number: H01L21/31116 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32513 ,  H01J37/32577 ,  H01J37/32623 ,  H01J37/32651 ,  H01J37/32871 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/30655 ,  H01L27/108 ,  H01L27/115

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition.

公开(公告)号：US09399819B2

公开(公告)日：2016-07-26

申请号：US13751282

申请日：2013-01-28

Applicant: ASM IP Holding B.V.

Inventor： Hyun-Kyu Cho

IPC: C23C16/52 ,  C23C16/455 ,  H01J37/32

CPC classification number: C23C16/513 ,  C23C16/45536 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32174 ,  H01J37/32899

Abstract: A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reactors; a plurality of gas supply units connected to the plurality of reactors; and a plurality of plasma supply units connected to the plurality of reactors. Each of the plasma supply units includes: a plasma power supplier; a plurality of diodes connected to the plasma power supplier; and a reverse voltage driver connected to the plurality of diodes through respectively corresponding switches.

Abstract translation: 根据本发明的示例性实施例的沉积设备包括多个反应器; 连接到所述多个反应器的多个气体供给单元; 以及与多个反应器连接的多个等离子体供给单元。 每个等离子体供应单元包括：等离子体供电器; 连接到等离子体电源的多个二极管; 以及通过分别对应的开关连接到所述多个二极管的反向电压驱动器。

公开(公告)号：US20160181117A1

公开(公告)日：2016-06-23

申请号：US14612095

申请日：2015-02-02

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Shashank C. Deshmukh ,  Eric A. Hudson ,  Tom Kamp ,  Samantha Tan ,  Gerardo Adrian Delgadino

IPC: H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  H01L21/263

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32899 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/76897

Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Abstract translation: 本文的实施例涉及用于蚀刻电介质材料中凹陷特征的方法和装置。 在各种实施例中，在两个蚀刻操作中形成凹陷特征。 第一蚀刻操作部分地蚀刻特征并且可以在配置成产生电容耦合等离子体的反应器中进行。 第一蚀刻操作可能在底层半导体材料由于穿过半导体材料顶部的电介质的离子穿透而经受显着的损坏之前结束。 第二蚀刻操作可以在配置成产生电感耦合等离子体的反应器中进行。 第一和第二蚀刻操作本身可以是多步循环过程。

公开(公告)号：US20160141210A1

公开(公告)日：2016-05-19

申请号：US15005700

申请日：2016-01-25

Applicant: Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to for corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 半导体晶片通过沟槽被等离子体蚀刻以用于相应的沟槽延伸并且对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。

公开(公告)号：US20160071702A1

公开(公告)日：2016-03-10

申请号：US14773573

申请日：2013-10-29

Applicant: Shimadzu Corporation

Inventor： Masayasu SUZUKI ,  Yosuke MORIMOTO

IPC: H01J37/32

CPC classification number: H01J37/32669 ,  C23C14/325 ,  H01J37/32055 ,  H01J37/32357 ,  H01J37/32568 ,  H01J37/32596 ,  H01J37/3266 ,  H01J37/32899 ,  H01J2237/002 ,  H01J2237/006 ,  H01J2237/06375 ,  H01J2237/152 ,  H01J2237/162 ,  H01J2237/327 ,  H01J2237/3326

Abstract: An arc-plasma film formation device includes a film formation chamber in which a substrate to be treated is stored, a plasma chamber in which at least a part of a target is stored, the plasma chamber being configured to be connected to the film formation chamber, and a plurality of hollow coils configured to generate a continuous line of magnetic force between the target and the film formation chamber and having at least one curved section, the plurality of hollow coils being arrange in the plasma chamber and covered by an outer coat made of a non-magnetic metal. Plasma containing ions derived from the target material and generated in the plasma chamber as a result of arc discharge is transported from the target to the substrate by passing an inside of the plurality of hollow coils.

Abstract translation: 电弧等离子体成膜装置包括：成膜室，其中存储有待处理的基板;等离子体室，其中存储有至少一部分靶;等离子体室被配置为连接到成膜室 以及多个中空线圈，其被配置为在所述靶和成膜室之间产生连续的磁力线，并且具有至少一个弯曲部分，所述多个中空线圈布置在所述等离子体室中并被外部涂层覆盖 的非磁性金属。 通过使多个中空线圈的内部通过，从目标材料产生并在等离子体室中产生的由于电弧放电而产生的等离子体从目标物传送到基板。