公开(公告)号：US5121299A

公开(公告)日：1992-06-09

申请号：US459087

申请日：1989-12-29

Applicant: Richard F. Frankeny ,  Karl Hermann

Inventor： Richard F. Frankeny ,  Karl Hermann

IPC: H01L23/498 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/462 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H05K3/4084 ,  H01L2224/16 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/09318 ,  H05K2201/096 ,  H05K2203/1461 ,  H05K2203/1572 ,  H05K3/28 ,  H05K3/32 ,  H05K3/4641 ,  H05K3/4647

Abstract: A multi-level circuit structure is provided which includes a plurality of overlying substrates, each having at least one conductive core. A plurality of imprinted depressions are formed in each substrate, each depression having a convex surface and a concave surface. Dielectric coatings are utilized to provide insulation between adjacent substrates and by selectively placing a conductive mass between selected overlying imprinted depressions an electrical connection may be formed between adjacent imprinted depressions wherein selected portions of one substrate may be electrically coupled to selected portions of a second substrate.

公开(公告)号：US3832602A

公开(公告)日：1974-08-27

申请号：US28444972

申请日：1972-08-28

Applicant: SIEMENS AG

Inventor： SCHAFF U ,  KAISER W ,  ENGELHARD D ,  HOFMANN H

IPC: H05K1/02 ,  H05K5/00

CPC classification number: H05K1/0233 ,  H05K1/0215 ,  H05K1/0227 ,  H05K1/0231 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09972 ,  H05K2201/1006 ,  H05K2201/10166

Abstract: A print for control modules of contact-free control and regulating systems comprising an insulating carrier plate having one portion of one surface adjacent the control inputs provided with a plurality of anti-interference filters. The number of filters is the same as the number of control inputs. The other portion of the one surface of the plate is provided with the same number of threshold value stages connected to the filters. The other surface of the carrier plate has a metal layer thereon which is electrically interrupted in accordance with the boundary between the first and second portions of the one surface thereof. The portion of the layer corresponding to the first portion is connected to ground and the portion of the layer corresponding to the second portion is connected to a reference potential.

Abstract translation: 一种无接触式控制和调节系统的控制模块的打印件，包括绝缘载板，该绝缘载板具有与设置有多个抗干扰滤波器的控制输入相邻的一个表面的一部分。 滤波器的数量与控制输入的数量相同。 板的一个表面的另一部分设置有连接到过滤器的相同数量的阈值级。 载体板的另一个表面上具有金属层，该金属层根据其一个表面的第一和第二部分之间的边界被电中断。 对应于第一部分的层的部分连接到地面，并且对应于第二部分的层的部分连接到参考电位。

公开(公告)号：US20180352689A1

公开(公告)日：2018-12-06

申请号：US15990712

申请日：2018-05-28

Applicant: GE Embedded Electronics Oy

Inventor： Risto Tuominen

IPC: H05K9/00 ,  H01L23/00 ,  H05K1/18

CPC classification number: H05K9/0081 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/92144 ,  H01L2924/01002 ,  H01L2924/01003 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/185 ,  H05K2201/0723 ,  H05K2201/09318 ,  H05K2201/10674 ,  H01L2924/00

Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component with contact terminals and conducting lines in a first wiring layer. There is also a dielectric between the component and the first wiring layer such that the component is embedded in the dielectric. Contact elements provide electrical connection between at least some of the contact terminals and at least some of the conducting lines. The electronic module also comprises a second wiring layer inside the dielectric. The second wiring layer comprises a conducting pattern that is at least partly located between the component and the first wiring layer and provides EMI protection between the component and the conducting lines.

公开(公告)号：US20180168039A1

公开(公告)日：2018-06-14

申请号：US15825563

申请日：2017-11-29

Applicant: CANON KABUSHIKI KAISHA

Inventor： Takashi Numagi ,  Youhei Tazawa ,  Shoji Matsumoto

IPC: H05K1/11 ,  H01L23/48 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/48 ,  H01L2224/16225 ,  H05K1/0216 ,  H05K1/0218 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09627

Abstract: Provided is a printed wiring board including: a plurality of inner layers including a ground layer and a power supply layer; and a plurality of ground vias and a plurality of power supply vias each provided to penetrate at least the ground layer and the power supply layer in a thickness direction of the printed wiring board, a ground potential being applied to the plurality of ground vias at the ground layer, and a power supply potential being applied to the plurality of power supply vias at the power supply layer. In a top view from a direction perpendicular to the printed wiring board, a distance between vias to which the same potential is applied is shorter than a distance between vias to which different potentials are applied.

公开(公告)号：US20160150639A1

公开(公告)日：2016-05-26

申请号：US14947065

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Mark W. Gailus ,  Marc B. Cartier, JR. ,  Vysakh Sivarajan ,  David Levine

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers; an antipad of a first type around and between the first and second signal vias in one or more of the attachment layers; and antipads of a second type around the first and second signal vias in at least one routing layer adjacent to the breakout layer.

Abstract translation: 印刷电路板包括多个层，包括附着层和布线层; 形成差分信号对的第一和第二信号通孔，第一和第二信号通孔延伸穿过连接层并连接到路由层的突围层上的各个信号迹线; 围绕一个或多个附着层中的第一和第二信号通孔之间和第一信号通路之间的第一类型的止动件; 以及围绕与突出层相邻的至少一个路由层中的第一和第二信号通孔周围的第二类型的反码器。

公开(公告)号：US08760815B2

公开(公告)日：2014-06-24

申请号：US12149903

申请日：2008-05-09

Applicant: Jun Ishii ,  Takahiko Yokai

Inventor： Jun Ishii ,  Takahiko Yokai

IPC: G11B5/48 ,  H05K1/02 ,  H05K1/05 ,  H05K3/46

CPC classification number: H05K1/0253 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/056 ,  H05K3/4644 ,  H05K2201/09081 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: The wired circuit board includes a metal supporting board, a metal foil formed on the metal supporting board, a first insulating layer formed on the metal supporting board so as to cover the metal foil, and a conductive pattern formed on the first insulating layer and having a plurality of wires. The metal foil is arranged along a lengthwise direction of each of the wires so as not to be opposed to part of the wires in a thickness direction and so as to be opposed to a remainder of the wires in the thickness direction.

Abstract translation: 布线电路板包括金属支撑板，形成在金属支撑板上的金属箔，形成在金属支撑板上以覆盖金属箔的第一绝缘层和形成在第一绝缘层上的导电图案，并且具有 多条电线。 金属箔沿着每条电线的长度方向布置，以便在厚度方向上不与电线的一部分相对，并且在厚度方向上与其余电线相对。

公开(公告)号：US08576567B2

公开(公告)日：2013-11-05

申请号：US12735415

申请日：2009-01-13

Applicant: Tatsuya Katoh ,  Takuya Sugiyama ,  Yasunori Chikawa

Inventor： Tatsuya Katoh ,  Takuya Sugiyama ,  Yasunori Chikawa

IPC: H05K7/20 ,  H05K7/00 ,  H01L23/34 ,  H01L23/495

CPC classification number: H01L23/3735 ,  G02F1/13452 ,  H01L23/36 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/50 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H05K1/0209 ,  H05K1/0271 ,  H05K1/189 ,  H05K3/361 ,  H05K2201/09318 ,  H05K2201/09681 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: A COF includes, in at least one embodiment, a heat dissipating material on a back surface of an insulating film. The heat dissipating material has a slit for reducing a degree of thermal expansion. Thus, at least one embodiment of the invention provides the COF in which deformation and disconnection of wiring are prevented.

Abstract translation: COF在至少一个实施例中包括在绝缘膜的背面上的散热材料。 散热材料具有用于降低热膨胀度的狭缝。 因此，本发明的至少一个实施例提供了防止布线变形和断开的COF。

公开(公告)号：US08569629B2

公开(公告)日：2013-10-29

申请号：US12768258

申请日：2010-04-27

Applicant: Tadao Ookawa ,  Mitsuru Honjo ,  Daisuke Yamauchi

Inventor： Tadao Ookawa ,  Mitsuru Honjo ,  Daisuke Yamauchi

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/16 ,  H05K1/18 ,  H05K7/00 ,  H01B7/08

CPC classification number: H05K1/0245 ,  H05K1/0393 ,  H05K3/28 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: An FPC board includes a base insulating layer. A plurality of wiring traces are formed on the base insulating layer. The adjacent wiring traces are arranged at a distance d from each other, and each wiring trace has a predetermined width and a thickness t1. Each transmission line pair is constituted by the two adjacent wiring traces of the plurality of wring traces. A ratio of the thickness t1 of the wiring trace to the distance d between the adjacent wiring traces is set to 0.8 or more. A cover insulating layer may be formed on the base insulating layer to cover the wiring traces. A metal layer having a predetermined thickness may be provided on a back surface of the base insulating layer. Furthermore, a differential impedance of each transmission line pair may be set to 100 Ω.

Abstract translation: FPC基板包括基底绝缘层。 在基底绝缘层上形成多个布线迹线。 相邻的布线轨迹彼此间距离设置，每个布线迹线具有预定的宽度和厚度t1。 每个传输线对由多个连接迹线的两个相邻的布线迹线构成。 布线迹线的厚度t1与相邻布线之间的距离d的比率设定为0.8以上。 覆盖绝缘层可以形成在基底绝缘层上以覆盖布线迹线。 可以在基底绝缘层的背面上设置具有预定厚度的金属层。 此外，每个传输线对的差分阻抗可以被设置为100Ω。

公开(公告)号：US08405468B2

公开(公告)日：2013-03-26

申请号：US13416794

申请日：2012-03-09

Applicant: Sergey V. Uchaykin

Inventor： Sergey V. Uchaykin

IPC: H01P1/203

CPC classification number: H01P1/2039 ,  H01P1/227 ,  H05K1/0224 ,  H05K1/0234 ,  H05K1/09 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09318 ,  H05K2201/09663

Abstract: An electronic filtering device includes continuous trace on a dielectric substrate and a dissipation layer communicatively coupled to the trace. The dissipation layer may include disconnected metal particles, which may be embedded in a substrate, for example in an epoxy. The continuous trace may be meandering, for example crenulated, coil or spiral signal path. At least a second continuous trace may be spaced from the first by the substrate, and conductively coupled by a via. The electronic filtering device may be used in one or more printed circuit boards (PCBs) that form stages of an input/output system.

Abstract translation: 电子滤波装置包括电介质基底上的连续迹线和与迹线通信耦合的耗散层。 耗散层可以包括分离的金属颗粒，其可以嵌入在基底中，例如环氧树脂中。 连续的迹线可能是曲折的，例如曲线，线圈或螺旋信号路径。 至少第二连续迹线可以与第一连续迹线间隔开，并且由通孔导电耦合。 电子滤波装置可以用于形成输入/输出系统阶段的一个或多个印刷电路板（PCB）中。

公开(公告)号：US08350158B2

公开(公告)日：2013-01-08

申请号：US12507551

申请日：2009-07-22

Applicant: Yechung Chung ,  Chulwoo Kim ,  Eunseok Song ,  Kyoungsei Choi

Inventor： Yechung Chung ,  Chulwoo Kim ,  Eunseok Song ,  Kyoungsei Choi

IPC: H05K1/00

CPC classification number: H05K1/0216 ,  H01L23/4985 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/114 ,  H05K1/189 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.

Abstract translation: 示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域的上表面的膜，所述芯片安装区域还包括内部区域和周边区域，所述膜还包括下表面，以及穿透所述膜的通孔， 所述通孔位于所述内部区域中，所述膜的上表面上的上金属层连接到半导体芯片的电极凸块，并且在所述膜的下表面上的下金属层。 示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域，下表面和通孔的通孔的上表面的膜，在膜的上表面上的上金属层，并连接到膜的电极凸块 半导体芯片以及下部金属层，通孔位于芯片安装区域的外侧。 示例性实施例涉及包括带布线基板的封装。