公开(公告)号：US06842344B1

公开(公告)日：2005-01-11

申请号：US10390383

申请日：2003-03-17

Applicant: Robert Fix ,  Daniel A. Jochym ,  Christian E. Shenberger

Inventor： Robert Fix ,  Daniel A. Jochym ,  Christian E. Shenberger

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K2201/09336

Abstract: A printed circuit board having a dielectric layer is disclosed. At least one signal trace is disposed adjacent a first surface of the dielectric layer in a first signal area. A reference plane is disposed adjacent a second surface of the dielectric layer in a first reference area positioned opposite the first signal area. The reference plane is configured to carry a reference potential for signals on the signal trace. At least one other signal trace is disposed adjacent the second surface of the dielectric layer in a second signal area and coupled to the signal trace in said first signal area. A second reference plane is disposed adjacent the first surface of the first dielectric layer in a second reference area positioned opposite the second signal area. The second reference plane is configured to carry the reference potential for signals on the other signal trace.

Abstract translation: 公开了一种具有电介质层的印刷电路板。 在第一信号区域中，邻近电介质层的第一表面设置至少一个信号迹线。 在与第一信号区域相对定位的第一参考区域中，在电介质层的第二表面附近设置参考平面。 参考平面被配置为对信号迹线上的信号携带参考电位。 至少一个其它信号迹线被布置在第二信号区域中与电介质层的第二表面相邻并且耦合到所述第一信号区域中的信号迹线。 在与第二信号区域相对定位的第二参考区域中，第二参考平面设置在第一介电层的第一表面附近。 第二参考平面被配置为对另一信号迹线上的信号携带参考电位。

公开(公告)号：US06804353B2

公开(公告)日：2004-10-12

申请号：US09896809

申请日：2001-06-29

Applicant: Paul W. Schmokel

Inventor： Paul W. Schmokel

IPC: H04M100

CPC classification number: H05K1/0216 ,  H04Q1/06 ,  H04Q1/14 ,  H04Q2201/10 ,  H04Q2201/12 ,  H04Q2201/14 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09336

Abstract: A telecommunications device including a plurality of splitter cards mounted in a chassis, a circuit board, and plurality of card edge connectors for providing electrical connections between the splitter cards and the circuit board, and POTS, LINE, and DATA connectors. The circuit board includes three layers, each layer having tracings that electrically connect at least one POTS, LINE, or DATA connector to at least one of the card edge connector. A center layer includes a grounding plane that is adapted to reduce cross-talk between tracings on a top layer and tracings on a bottom layer. The grounding plane is co-planar with tracings on the center layer such that the grounding plane adds additional thickness to the center layer.

Abstract translation: 一种电信设备，包括安装在机箱中的多个分配卡，电路板，用于提供分配卡和电路板之间的电连接的多个卡缘连接器以及POTS，LINE和DATA连接器。 电路板包括三层，每层具有将至少一个POTS，LINE或DATA连接器电连接到至少一个卡缘连接器的追踪。 中心层包括接地平面，其适于减少顶层上的迹线与底层上的跟踪之间的串扰。 接地平面与中心层上的跟踪共面，使得接地平面不增加中心层的附加厚度。

公开(公告)号：US06800814B2

公开(公告)日：2004-10-05

申请号：US10046163

申请日：2002-01-16

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K103

CPC classification number: H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

Abstract: A multi-layered printed wiring board capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

Abstract translation: 一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的布线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

公开(公告)号：US06784780B2

公开(公告)日：2004-08-31

申请号：US10217557

申请日：2002-08-13

Applicant: Shigeru Osada

Inventor： Shigeru Osada

IPC: H01F500

CPC classification number: H05K1/165 ,  H01F5/003 ,  H01F17/0033 ,  H05K3/222 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/097 ,  H05K2201/10636 ,  H05K2203/171 ,  Y02P70/611

Abstract: A coupling adjusting structure for a double-tuned circuit contains first and second coils that are configured such that a pair of first conductive patterns formed on a first surface of a printed circuit and a corresponding pair of second conductive patterns formed on a second surface of the printed circuit board are connected via corresponding connecting conductors. One end of the first coil and the corresponding end of the second coil are disposed close to each other. A first ground conductive pattern is disposed at least on the first surface of the printed circuit. A first jumper connected to the first ground conductive pattern is disposed between the first and second coils to adjust an inductive coupling of the double-tuned circuit.

Abstract translation: 用于双调谐电路的耦合调节结构包括第一和第二线圈，其被配置为使得形成在印刷电路的第一表面上的一对第一导电图案和形成在第二表面的相应的一对第二导电图案 印刷电路板通过相应的连接导体连接。 第一线圈的一端和第二线圈的对应端部彼此靠近地设置。 第一接地导电图案至少设置在印刷电路的第一表面上。 连接到第一接地导电图案的第一跨接件设置在第一和第二线圈之间，以调整双调谐电路的电感耦合。

公开(公告)号：US20040163848A1

公开(公告)日：2004-08-26

申请号：US10727992

申请日：2003-12-05

Applicant: SEIKO EPSON CORPORATION

Inventor： Eiji Takagi ,  Yuichi Kojima

IPC: H05K001/00 ,  H05K001/11

CPC classification number: H05K1/0224 ,  H05K1/0227 ,  H05K2201/09336 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09781 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: To manufacture a printed wiring board, the positions and shapes of several slits to satisfy UL796 standard, etc., formed in a ground or power supply plane are determined so that each slit is formed in a section corresponding to a ground guard in a portion containing a signal line and a signal line gap.

Abstract translation: 为了制造印刷电路板，确定形成在接地或电源平面中的符合UL796标准等的几个狭缝的位置和形状，使得每个狭缝形成在与包含 信号线和信号线间隙。

公开(公告)号：US20040155712A1

公开(公告)日：2004-08-12

申请号：US10772314

申请日：2004-02-06

Inventor： Tatsunobu Inamoto ,  Jiro Miyahara

IPC: H03F003/60

CPC classification number: H05K3/222 ,  H03F3/19 ,  H03F3/60 ,  H05K1/0219 ,  H05K1/0237 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A high-frequency circuit comprises a substrate having an electronic component on an obverse side thereof, a first ground pattern formed on almost an entire reverse side of the substrate, a microstrip line formed on the obverse side of the substrate, and a bias line connected to the electronic component on the obverse side of the substrate and formed continuously on the obverse side and the reverse side of the substrate so as to cross the microstrip line on the reverse side of the substrate in plan view so as to supply a bias voltage to the electronic component, wherein the first ground pattern is formed so as to circumvent the bias line formed on the reverse side of the substrate, a portion of the first ground pattern that circumvents the bias line on the reverse side of the substrate is continuously formed on the obverse side of the substrate as a second ground pattern so as to divide the microstrip line in two parts, and a chip jumper is arranged to bridge the two divided parts of the microstrip line over the second ground pattern so as to connect the divided microstrip line electrically.

Abstract translation: 高频电路包括在其正面上具有电子部件的基板，形成在基板的几乎整个背面的第一接地图案​​，形成在基板的正面的微带线和连接的偏置线 到基板的正面的电子部件，并且在基板的正面和反面上连续地形成，以在平面图中与基板的相反侧的微带线交叉，以便将偏置电压提供给 所述电子部件，其中形成所述第一接地图案​​以避开形成在所述基板的相反侧上的所述偏置线，所述第一接地图案​​的绕所述基板的相反侧的所述偏置线的部分连续地形成在 将基板的正面作为第二接地图案，以将微带线分成两部分，并且设置芯片跳线以将两个分开的部分 e微带线在第二接地图案上，以便电连接分开的微带线。

公开(公告)号：US20040119553A1

公开(公告)日：2004-06-24

申请号：US10695732

申请日：2003-10-28

Applicant: CANON KABUSHIKI KAISHA

Inventor： Shinichi Nishimura

IPC: H01P001/26

CPC classification number: H05K1/0246 ,  H01P1/26 ,  H05K1/0231 ,  H05K1/0245 ,  H05K1/181 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A center-tap termination circuit which includes two resistors having the same resistance, which are serially connected between forward and return transmission lines, where the forward and return transmission lines constitute a differential signal transmission line. A capacitor is connected between a connector that interconnects the two resistors and a GND of a printed circuit board. The forward and return transmission lines are substantially equidistant from each other along their lengths. The resistors and the capacitor are arranged outside the forward and return transmission lines. The connector is provided intersecting, in three-dimensional space, the forward and return transmission lines, such as being formed by a jumper bridging the two lines, or by being formed on a different layer of a multilayer printed circuit board. Variations in the differential impedance are suppressed, and the transmission return/transmission forward characteristics of differential signals are substantially matched. The differential impedance matching is achieved, and high-quality signal waveforms are maintained. Not only noise emitted due to differential mode current components, but also noise emitted due to common mode current components are suppressed.

Abstract translation: 中心抽头终端电路，其包括具有相同电阻的两个电阻，串联连接在正向和返回传输线之间，其中正向和返回传输线构成差分信号传输线。 电容器连接在连接两个电阻器的连接器和印刷电路板的GND之间。 前进和后退传输线沿其长度基本上等距离。 电阻器和电容器布置在正向和返回传输线的外部。 连接器在三维空间中被提供在正向和返回传输线上，例如由跨接两条线的跨接线形成，或者通过形成在多层印刷电路板的不同层上。 抑制差分阻抗的变化，差分信号的发送返回/发送正向特性基本上匹配。 实现了差分阻抗匹配，并保持了高质量的信号波形。 不仅由于差分电流分量而产生的噪声，而且由共模电流分量引起的噪声也被抑制。

公开(公告)号：US06521843B1

公开(公告)日：2003-02-18

申请号：US09304631

申请日：1999-05-04

Applicant: Kenji Kohya

Inventor： Kenji Kohya

IPC: H05K103

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09336 ,  H05K2201/09627 ,  H05K2201/09845

Abstract: A multilayer printed circuit board enables needless electro-magnetic radiation to be suppressed. Interlayer insulation materials are arranged in layer-built constitution between respective layers of a mixed wiring layer of a first signal and/or a power supply wiring, a first ground layer, a second ground layer, and a mixed wiring layer of a second signal and/or a power supply wiring. A through-hole for connecting the ground layers with each other is provided adjacently to a through-hole for connecting the signal and/or the power supply between these layers. According to the constitution, a return circuit current route of the signal and the power supply to the ground layers is secured. As a result, a loop made by the current becomes small, thus needless radiation of electro-magnetic wave is capable of being suppressed.

Abstract translation: 多层印刷电路板能够抑制不必要的电磁辐射。 层间绝缘材料以第一信号和/或电源布线，第一接地层，第二接地层和第二信号的混合布线层的混合布线层的各层之间的层间构造布置，并且 /或电源接线。 用于连接接地层的通孔相邻设置用于连接这些层之间的信号和/或电源的通孔。 根据该结构，确保信号的回路电流路径和对地层的电力供应。 结果，由电流产生的环路变小，因此能够抑制电磁波的不必要的辐射。

公开(公告)号：US20030024732A1

公开(公告)日：2003-02-06

申请号：US10254851

申请日：2002-09-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ryoji Ninomiya

IPC: H05K007/06

CPC classification number: H05K1/0246 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09909 ,  H05K2201/09936 ,  H05K2201/10022 ,  H05K2201/10636 ,  H05K2203/161 ,  Y02P70/611

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

公开(公告)号：US20030002656A1

公开(公告)日：2003-01-02

申请号：US09896809

申请日：2001-06-29

Applicant: ADC Telecommunications, Inc.

Inventor： Paul W. Schmokel

IPC: H04M003/00 ,  H04M005/00

CPC classification number: H05K1/0216 ,  H04Q1/06 ,  H04Q1/14 ,  H04Q2201/10 ,  H04Q2201/12 ,  H04Q2201/14 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09336

Abstract: A telecommunications device including a plurality of splitter cards mounted in a chassis. The device also includes a circuit board and plurality of card edge connectors for providing electrical connections between the splitter cards and the circuit board. The device further includes POTS connectors, LINE connectors and DATA connectors. The circuit board includes a first layer having first tracings that electrically connect contacts of at least one of the POTS, LINE or DATA connectors to at least one of the card edge connectors; a second layer having second tracings that electrically connect contacts of at least one of the POTS, LINE or DATA connectors to at least one of the card edge connectors; and a third layer having third tracings that electrically connect contacts of at least one of the POTS, LINE or DATA connectors to at least one of the card edge connectors. The second layer is positioned between the first and third layers. A majority of the second layer is covered by a grounding plane. The grounding plane and the second tracings are co-planar such that the grounding plane adds no additional thickness to the second layer. The grounding plane is positioned between the first and third tracings to reduce cross-talk between the first and third tracings.

Abstract translation: 一种电信设备，包括安装在底盘中的多个分配卡。 该装置还包括电路板和用于提供分配卡和电路板之间的电连接的多个卡缘连接器。 该设备还包括POTS连接器，LINE连接器和DATA连接器。 电路板包括具有第一跟踪的第一层，其将POTS，LINE或DATA连接器中的至少一个的触点电连接到至少一个卡缘连接器; 具有将POTS，LINE或DATA连接器中的至少一个的触点电连接到至少一个卡缘连接器的第二跟踪的第二层; 以及第三层，其具有将POTS，LINE或DATA连接器中的至少一个的触点电连接到所述卡缘连接器中的至少一个的第三跟踪。 第二层位于第一层和第三层之间。 大多数第二层被接地平面覆盖。 接地平面和第二跟踪是共平面的，使得接地平面不向第二层增加额外的厚度。 接地平面位于第一和第三迹线之间，以减少第一和第三迹线之间的串扰。