公开(公告)号：US07020960B2

公开(公告)日：2006-04-04

申请号：US10762860

申请日：2004-01-22

Applicant: Stephen Nelson ,  Donald White

Inventor： Stephen Nelson ,  Donald White

IPC: H05K3/02

CPC classification number: H05K3/242 ,  H05K1/0298 ,  H05K1/117 ,  H05K3/0047 ,  H05K3/0052 ,  H05K2201/0949 ,  H05K2203/0228 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Systems and methods for plating printed circuit boards. Traces are formed using internal and external layers of a printed circuit board from conductive paths including contact pads to a side edge of the printed circuit board. The traces are connected with a plating bar to form a single conductive path that permits all conductive paths to be plated at the same time. When the plating bar is removed, the traces are severed to electrically isolate the various conductive paths. Traces are not present at a front edge of the printed circuit board by the contact pads. A small hole is drilled through traces used to plate transmission lines such that the traces do not affect the transmission characteristics of the transmission lines.

Abstract translation: 印刷电路板电镀系统和方法。 使用印刷电路板的内部和外部层从包括接触焊盘的导电路径到印刷电路板的侧边缘形成迹线。 迹线与电镀条连接以形成允许所有导电路径同时镀覆的单个导电路径。 当去除电镀棒时，切断电路以电绝缘各种导电路径。 轨迹不通过接触垫存在于印刷电路板的前边缘处。 通过用于铺板传输线的轨迹钻出一个小孔，使得轨迹不影响传输线的传输特性。

公开(公告)号：US20060050491A1

公开(公告)日：2006-03-09

申请号：US11219114

申请日：2005-09-02

Applicant: Seiji Hayashi ,  Hideho Inagawa

Inventor： Seiji Hayashi ,  Hideho Inagawa

IPC: H05K7/08

CPC classification number: H05K1/0231 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract translation: 多层印刷电路板包括：第一表面层，包括半导体集成电路;第二表面层，包括旁路电容器，并且与第一表面层相对;主电源布线层;以及第一表面层， 和第二表面层。 在多层印刷电路板中，旁路电容器的一个端子连接到从主电源布线层到半导体集成电路的电源端子的布线路径的中点，并且从第一布线路径的阻抗 到旁路电容器的端子的主电源布线层高于从旁路电容器的端子到半导体集成电路的电源端子的第二布线路径的阻抗。

公开(公告)号：US06927663B2

公开(公告)日：2005-08-09

申请号：US10625827

申请日：2003-07-23

Applicant: Tom Iverson ,  Bart Carey ,  Robert S. Harguth

Inventor： Tom Iverson ,  Bart Carey ,  Robert S. Harguth

IPC: A61N1/08 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F30/16 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01F5/00

CPC classification number: H01F41/08 ,  A61N1/08 ,  A61N1/378 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/02 ,  H01F27/04 ,  H01F27/2804 ,  H01F27/292 ,  H01F30/16 ,  H01F38/42 ,  H01F41/10 ,  H05K1/141 ,  H05K1/18 ,  H05K3/3447 ,  H05K2201/0949 ,  H05K2201/1003 ,  Y10T29/4902

Abstract: A method of forming a surface mount transformer. The method comprises winding insulated wire around a magnetic core to form at least one secondary transformer coil, winding insulated wire around the magnetic core to form at least one primary transformer coil, attaching wire ends of the at least one primary coil to at least first and second vias of a printed circuit board (PCB), attaching wire ends of the at least one secondary coil to at least third and fourth vias of the PCB, affixing the coils and the magnetic core to the first side of the PCB, and attaching the coil wire ends flush to a surface of the vias on the second side of the PCB.

Abstract translation: 一种形成表面贴装变压器的方法。 该方法包括围绕磁芯缠绕绝缘电线以形成至少一个次级变压器线圈，围绕磁芯缠绕绝缘线以形成至少一个初级变压器线圈，将至少一个初级线圈的线端附接至至少第一和 印刷电路板（PCB）的第二通孔，将至少一个次级线圈的线端连接到PCB的至少第三和第四通孔，将线圈和磁芯固定到PCB的第一侧，并且将 线圈线与PCB的第二面的通孔表面齐平。

公开(公告)号：US20050139383A1

公开(公告)日：2005-06-30

申请号：US10946379

申请日：2004-09-20

Applicant: Harold Kent ,  James Levante

Inventor： Harold Kent ,  James Levante

IPC: H05K1/11 ,  H05K3/06 ,  H05K3/24 ,  H05K3/28 ,  H05K3/42 ,  H01R12/00 ,  G03G13/14 ,  H05K1/03

CPC classification number: H02J7/0045 ,  H05K1/11 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0373 ,  H05K2201/0949 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/072

Abstract: A power transfer pad, having: a non-conductive board having a top and a bottom; a plurality of conductive substrate sections disposed across the top of the non-conductive board; at least one conducting element disposed on each of the conductive substrate sections; a plurality of electrical contacts on the bottom of the non-conductive board, wherein each of the electrical contacts on the bottom of the non-conductive board are in electrical communication with one of the conductive substrate sections on the top of the non-conductive board.

Abstract translation: 一种功率传递垫，具有：具有顶部和底部的非导电板; 设置在所述非导电板的顶部的多个导电基板部分; 至少一个导电元件设置在每个导电基底部分上; 在所述非导电板的底部上的多个电触头，其中所述非导电板的底部上的每个所述电触点与所述非导电板的顶部上的导电衬底部分中的一个电连通 。

公开(公告)号：US20050017054A1

公开(公告)日：2005-01-27

申请号：US10625827

申请日：2003-07-23

Applicant: Tom Iverson ,  Bart Carey ,  Robert Harguth

Inventor： Tom Iverson ,  Bart Carey ,  Robert Harguth

IPC: A61N1/08 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F30/16 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  B23K31/02

CPC classification number: H01F41/08 ,  A61N1/08 ,  A61N1/378 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/02 ,  H01F27/04 ,  H01F27/2804 ,  H01F27/292 ,  H01F30/16 ,  H01F38/42 ,  H01F41/10 ,  H05K1/141 ,  H05K1/18 ,  H05K3/3447 ,  H05K2201/0949 ,  H05K2201/1003 ,  Y10T29/4902

Abstract: A method of forming a surface mount transformer. The method comprises winding insulated wire around a magnetic core to form at least one secondary transformer coil, winding insulated wire around the magnetic core to form at least one primary transformer coil, attaching wire ends of the at least one primary coil to at least first and second vias of a printed circuit board (PCB), attaching wire ends of the at least one secondary coil to at least third and fourth vias of the PCB, affixing the coils and the magnetic core to the first side of the PCB, and attaching the coil wire ends flush to a surface of the vias on the second side of the PCB.

公开(公告)号：US20040245628A1

公开(公告)日：2004-12-09

申请号：US10753828

申请日：2004-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-Chung Chung

IPC: H01L023/48

CPC classification number: H01L22/32 ,  H01L23/49572 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0268 ,  H05K1/0393 ,  H05K2201/0949 ,  H05K2203/1545

Abstract: A tape package in which a test pad is formed on a reverse surface is provided. The test pad is disposed on a reverse surface of a base film through a through hole of the base film. Accordingly, shapes of the test pads are standardized so that a universal probe card can be used. A pitch between the test pads is wide so that the accuracy in an electric test of the tape package is increased. A total length of the tape package is reduced.

Abstract translation: 提供其中在反面上形成测试垫的带包装。 测试垫通过基膜的通孔设置在基膜的反面上。 因此，测试垫的形状被标准化，使得可以使用通用探针卡。 测试垫之间的间距是宽的，使得磁带封装的电测试的精度提高。 磁带封装的总长度减小。

公开(公告)号：US06767252B2

公开(公告)日：2004-07-27

申请号：US10267443

申请日：2002-10-09

Applicant: James L. McGrath ,  James P. Capadona ,  Daniel B. McGowan ,  Augusto P. Panella

Inventor： James L. McGrath ,  James P. Capadona ,  Daniel B. McGowan ,  Augusto P. Panella

IPC: H01R2370

CPC classification number: H05K1/117 ,  H01R12/721 ,  H01R13/6585 ,  H05K1/0219 ,  H05K2201/093 ,  H05K2201/0949 ,  H05K2201/0969 ,  H05K2201/09709 ,  H05K2201/09727

Abstract: A differential signal connector that is used for edge card application has a plurality of differential signal terminals and associated ground terminals arranged in “triplets”, i.e., distinct sets of three conductive terminals, each such triplet including a pair of differential signal terminals and one associated ground terminal. The ground terminal is flanked by the two differential signal terminals and each triplet is spaced apart from an adjacent triplet by a spacing which is greater than any single spacing between adjacent terminals within a triplet. Circuit boards to which such a connector is mounted are also disclosed and they have a particular pattern of termination traces, commonly taking the form of plated vias extending through the circuit board. These vias are arranged in a triangular pattern and the ground reference plane of the circuit board is provided with voids, one void being associated and encompassing a pair of the differential signal vias of a single terminal triplet. This reduces the capacitance of the signal vias and thereby increases the impedance of the circuit board within the launch area to lessen impedance discontinuities in the connector-circuit board interface.

Abstract translation: 用于边缘卡应用的差分信号连接器具有多个差分信号端子和以“三联体”排列的相关联的接地端子，即，三组导电端子的不同组合，每个这样的三联组件包括一对差分信号端子和一个相关联的 接地端。 接地端子侧面是两个差分信号端子，每个三极管与相邻的三通线隔开一个间隔，该间隔大于三线态内的相邻端子之间的任何单个间隔。 还公开了安装这种连接器的电路板，并且它们具有特定的端接迹线图案，通常采用延伸穿过电路板的电镀通孔的形式。 这些通孔被布置成三角形图案，并且电路板的接地参考平面设置有空隙，一个空隙相关联并且包围一对单个三端口的差分信号通路。 这减小了信号通路的电容，从而增加了发射区域内的电路板的阻抗，以减少连接器 - 电路板接口中的阻抗不连续性。

公开(公告)号：US20040035933A1

公开(公告)日：2004-02-26

申请号：US10440729

申请日：2003-05-19

Inventor： William H. Havens ,  Robert J. Hennick ,  John Izzo ,  Michael Robinson

IPC: G06K007/10 ,  G06K007/14

CPC classification number: G06K7/10584 ,  G06K7/10722 ,  G06K7/10801 ,  G06K7/10861 ,  G06K7/14 ,  H05K1/116 ,  H05K1/18 ,  H05K3/244 ,  H05K2201/09072 ,  H05K2201/09463 ,  H05K2201/0949 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2201/10121

Abstract: An optical reader including an image sensor, imaging optics, a short range aiming assembly, and a long range aiming assembly. The short range aiming assembly may comprise a plurality of LEDs. The long range aiming assembly may comprise a laser diode assembly which projects an aiming pattern that is readily visible at reading distances of several feet. The optical reader can be configured so that long range aiming assembly is enabled or disabled depending upon a present operating condition.

Abstract translation: 包括图像传感器，成像光学元件，短距离瞄准组件和远程瞄准组件的光学读取器。 短距离瞄准组件可以包括多个LED。 长距离瞄准组件可以包括激光二极管组件，其投射在几英尺的读取距离处容易看见的瞄准图案。 光学读取器可以被配置为使得远程瞄准组件被启用或禁用，这取决于当前的操作条件。

公开(公告)号：US06642136B1

公开(公告)日：2003-11-04

申请号：US09953525

申请日：2001-09-17

Applicant: Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.

Abstract translation: 提供了一种新的方法和芯片级封装。 衬底上的电接触点通过沉积在衬底上的钝化层和聚合物或弹性体的上层形成的开口露出。 屏障/种子层被沉积。 第一光致抗蚀剂掩模将该层覆盖并与接触垫相邻的势垒/种子层暴露。 屏蔽/种子层的暴露表面被电镀。 去除第一光致抗蚀剂掩模，产生第二光致抗蚀剂掩模以限定暴露阻挡层/种子层的表面积而不覆盖接触焊盘的焊料凸块。 产生焊料凸点，去除第二光致抗蚀剂掩模。 根据电镀蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸块的回流焊。

公开(公告)号：US20030068877A1

公开(公告)日：2003-04-10

申请号：US10225907

申请日：2002-08-21

Inventor： Larry D. Kinsman

IPC: H01L021/44

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.