公开(公告)号：US20170171957A1

公开(公告)日：2017-06-15

申请号：US14969514

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Nayandeep K. Mahanta ,  Joshua D. Heppner ,  Adel A. Elsherbini

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L23/34 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09854

Abstract: The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.

公开(公告)号：US20170094774A1

公开(公告)日：2017-03-30

申请号：US14866614

申请日：2015-09-25

Applicant: Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff

IPC: H05K1/02 ,  H05K3/22 ,  H05K3/30 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/028 ,  H05K1/0283 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/118 ,  H05K1/181 ,  H05K3/22 ,  H05K3/284 ,  H05K3/301 ,  H05K3/4691 ,  H05K2201/05 ,  H05K2201/057 ,  H05K2201/09263 ,  H05K2201/095 ,  H05K2203/1316

Abstract: Some forms relate to a stretchable computing device that includes a stretchable body; a first electronic component embedded within the stretchable body; a second electronic component embedded within the stretchable body; and wherein the first electronic component and the second electronic component are connected by stretchable electrical connectors that include vias. The stretchable electrical connectors are non-planar and/or may have a partial zig-zag shape and/or a partial coil shape. In some forms, the stretchable computing device further includes a textile attached to the stretchable body.

公开(公告)号：US09583459B2

公开(公告)日：2017-02-28

申请号：US14894558

申请日：2014-05-27

Applicant: Linxens Holding

Inventor： Severine Dieu-Gomont ,  Bertrand Hoveman

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/02 ,  H05K3/06 ,  H05K3/28 ,  G06K19/077 ,  H05K1/11

CPC classification number: H01L24/85 ,  G06K19/07769 ,  H01L23/49855 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49 ,  H01L2224/49109 ,  H01L2224/85 ,  H01L2224/85002 ,  H01L2924/00014 ,  H05K1/028 ,  H05K1/0296 ,  H05K1/11 ,  H05K1/115 ,  H05K3/06 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2201/095 ,  H05K2201/09509 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: The invention concerns a method for producing a printed circuit for a chip card module. This method involves producing two layers of electrically conductive material insulated from each other by a layer of insulating material, connection holes extending through the layer of insulating material and blocked by one of the layers of electrically conductive material, an area free of conductive material being provided in the other layer of electrically conductive material around the connection holes. The invention also concerns a printed circuit for a chip card produced using this method and a chip card module including such a printed circuit.

Abstract translation: 本发明涉及一种用于制造用于芯片卡模块的印刷电路的方法。 该方法涉及通过绝缘材料层彼此绝缘的两层导电材料制成，连接孔延伸穿过绝缘材料层并被导电材料层之一阻挡，提供了不含导电材料的区域 在连接孔周围的另一层导电材料中。 本发明还涉及使用该方法制造的芯片卡的印刷电路和包括这种印刷电路的芯片卡模块。

公开(公告)号：US20160007442A1

公开(公告)日：2016-01-07

申请号：US14838098

申请日：2015-08-27

Applicant: ISOLA USA CORP.

Inventor： Roland Schönholz

IPC: H05K1/02 ,  H05K1/11 ,  B32B37/06 ,  B32B37/10 ,  B32B27/08 ,  B32B15/08

CPC classification number: B32B15/08 ,  B32B5/024 ,  B32B5/26 ,  B32B15/14 ,  B32B15/20 ,  B32B37/0076 ,  B32B37/02 ,  B32B37/144 ,  B32B37/26 ,  B32B37/30 ,  B32B38/10 ,  B32B2260/023 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2305/076 ,  B32B2305/72 ,  B32B2305/74 ,  B32B2305/77 ,  B32B2307/41 ,  B32B2307/412 ,  B32B2310/0831 ,  B32B2457/08 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/118 ,  H05K1/147 ,  H05K3/429 ,  H05K3/4691 ,  H05K2201/0195 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/095 ,  Y10T428/24314 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/24612 ,  Y10T428/24802 ,  Y10T428/24851 ,  Y10T428/2486

Abstract: Prepregs having a UV curable resin layer located adjacent to a thermally curable resin layer wherein the UV curable resin layer includes at least one UV cured resin portion and at least one UV uncured resin as well as methods for preparing flexible printed circuit boards using the prepregs.

Abstract translation: 具有位于热固化树脂层附近的UV固化树脂层的预浸料，其中UV固化树脂层包括至少一个UV固化树脂部分和至少一种UV未固化树脂，以及制备使用该预浸料的柔性印刷电路板的方法。

公开(公告)号：US20150313017A1

公开(公告)日：2015-10-29

申请号：US14790302

申请日：2015-07-02

Applicant: MORGAN / WEISS TECHNOLOGIES INC.

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.

Abstract translation: 多层插入器衬底包括多层单个插入器衬底。 每个单个插入器衬底具有第一内插器互连阵列，每个插入器互连在插入器互连的第一阵列中对应于处理器互连阵列中的互连，插入器互连的第二阵列，插入器互连的第二阵列中的每个插入器互连 对应于电路基板上的电路互连阵列，以及与插入器互连的第一阵列中的至少一个互连相关联的插入器基板中的至少一个导电迹线。 导电迹线具有平行于插入器基板的平行部分，使得互连和第二插入器互连阵列中的相应的一个插入器互连之间不存在电连接。 每个单个插入器上的外围电路的连接阵列连接到至少一个导电迹线。

公开(公告)号：US20240244754A1

公开(公告)日：2024-07-18

申请号：US18559943

申请日：2022-06-14

Applicant: Mitsubishi Electric Corporation

Inventor： Yoshimichi SAITO ,  Yoshikazu TSUNODA ,  Kenta FUJII ,  Takashi KUMAGAI ,  Tomohito FUKUDA ,  Yuji SHIRAKATA

IPC: H05K1/18 ,  H05K3/00

CPC classification number: H05K1/184 ,  H05K3/0085 ,  H05K2201/066 ,  H05K2201/095 ,  H05K2201/10015 ,  H05K2201/10409 ,  H05K2203/1147

Abstract: A circuit device includes: a heat sink having an upper surface orthogonal to a first direction; a plurality of first partition plates attached to the upper surface and extending in a second direction orthogonal to the first direction; a plurality of second partition plates attached to the upper surface and extending in a third direction orthogonal to the first direction and the second direction; a circuit component; a substrate electrically connected to the circuit component; and a first heat transfer member. The circuit component is housed in a space surrounded by two adjacent first partition plates, two adjacent second partition plates, and the upper surface. The first heat transfer member is disposed between the first partition plate and the circuit component.

公开(公告)号：US20240186272A1

公开(公告)日：2024-06-06

申请号：US18218756

申请日：2023-07-06

Applicant: Hyundai Motor Company ,  Kia Corporation

Inventor： Myung III YOU ,  Jun Hee PARK

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H05K1/18

CPC classification number: H01L23/66 ,  H01L23/49541 ,  H01L24/48 ,  H05K1/189 ,  H01L2224/48137 ,  H01L2224/48175 ,  H05K2201/095

Abstract: A power module is provided. In the power module, electrical connection to the outside is enabled through a FPCB made to be flexible and deformable, and as terminals for signal transmission and wire bonding for connecting terminals are eliminated, insulation is ensured and the overall size is reduced.

公开(公告)号：US20240147617A1

公开(公告)日：2024-05-02

申请号：US18548458

申请日：2022-03-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takayoshi NIRENGI ,  Akihiro OISHI ,  Tsutomu AISAKA ,  Daisuke MATSUSHITA ,  Jumpei IWANAGA ,  Tadashi TOJO

IPC: H05K1/09 ,  H05K3/46

CPC classification number: H05K1/09 ,  H05K3/46 ,  H05K2201/0753 ,  H05K2201/095

Abstract: A wiring body disposed above a substrate including a conductor including: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. A lower layer included in the via electrode and located above the insulating layer and a lower layer included in the wiring include the same material.

公开(公告)号：US11842958B2

公开(公告)日：2023-12-12

申请号：US17697937

申请日：2022-03-18

Applicant: Chun-Ming Lin

Inventor： Chun-Ming Lin

IPC: H05K1/09 ,  H05K1/11 ,  H01L23/498 ,  C25D7/12 ,  H01L21/48 ,  C25D3/38 ,  H05K1/18

CPC classification number: H01L23/49866 ,  C25D3/38 ,  C25D7/12 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/09 ,  H05K1/112 ,  H05K1/18 ,  H05K2201/0332 ,  H05K2201/0364 ,  H05K2201/095 ,  H05K2201/09509

Abstract: The present disclosure provides a multilayer wiring structure, including a plurality of dielectric layers, a plurality of conductive wiring layers interleaved with the plurality of dielectric layers, wherein the plurality of conductive wiring layers includes copper-phosphorous alloys (such as Cu3P).

公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.