公开(公告)号：US20150042421A1

公开(公告)日：2015-02-12

申请号：US14521533

申请日：2014-10-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO

IPC: H01P3/00 ,  B32B38/04 ,  B32B37/12 ,  H01P11/00 ,  B32B37/02

CPC classification number: H01P3/003 ,  B32B37/02 ,  B32B37/12 ,  B32B38/04 ,  B32B2038/042 ,  B32B2307/204 ,  B32B2457/00 ,  H01P3/085 ,  H01P5/028 ,  H01P11/003 ,  H05K1/0221 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/028 ,  H05K1/147 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A laminated flat cable includes a laminate, a signal line for high-frequency signal transmission, a reference ground conductor, and an auxiliary ground conductor. The laminate includes a first base layer with first and second principal surfaces and a second base layer with third and fourth principal surfaces, and the second principal surface is opposed to the third principal surface. The signal line is located on the second principal surface. The reference ground conductor is located on the first principal surface and is opposite to the signal line. The auxiliary ground conductor is located on the third or fourth principal surface and is opposite to the signal line. The auxiliary ground conductor includes a plurality of openings arranged along the signal line.

Abstract translation: 叠层扁平电缆包括层压板，用于高频信号传输的信号线，参考接地导体和辅助接地导体。 层压体包括具有第一和第二主表面的第一基层和具有第三和第四主表面的第二基层，第二主表面与第三主表面相对。 信号线位于第二主表面上。 参考接地导体位于第一主表面上并与信号线相对。 辅助接地导体位于第三或第四主表面上，与信号线相对。 辅助接地导体包括沿信号线布置的多个开口。

公开(公告)号：US20150016069A1

公开(公告)日：2015-01-15

申请号：US14004443

申请日：2013-07-15

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.

Inventor： Jianyong Fu ,  Anle Hu ,  Xiaoping Tan

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K3/328 ,  H05K2201/09136 ,  H05K2201/093 ,  H05K2201/0969

Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a main body. A first surface of the main body is a connecting surface for electrical components. A second surface of the main body is a conductive cooper foil layer operating as ground wires. A plurality of grooves is arranged on the conductive cooper foil layer. The grooves pass through the conductive cooper foil layer to connect to the main body of the PCB. The thermal stress generated in the PCB welding process can be effectively released via the grooves. The inflation of the conductive cooper coil is relieved such that the PCB is prevented from being wrapped or cooper bubbling. In this way, the operation efficiency is enhanced and the manufacturing cost is reduced.

Abstract translation: 公开了印刷电路板（PCB）。 PCB包括主体。 主体的第一表面是用于电气部件的连接表面。 主体的第二表面是作为接地线操作的导电铜箔层。 多个凹槽布置在导电铜箔层上。 槽通过导电铜箔层连接到PCB的主体。 PCB焊接过程中产生的热应力可以通过槽有效释放。 释放导电铜线圈的膨胀，使得防止PCB被包裹或起泡。 这样，提高了运行效率，降低了制造成本。

公开(公告)号：US20150008012A1

公开(公告)日：2015-01-08

申请号：US14494994

申请日：2014-09-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi SASAKI

IPC: H01B7/08 ,  H01B3/30

CPC classification number: H01B7/0823 ,  H01B3/306 ,  H01P3/085 ,  H05K1/0221 ,  H05K1/0225 ,  H05K1/0253 ,  H05K1/028 ,  H05K2201/055 ,  H05K2201/09618 ,  H05K2201/0969

Abstract: A flat cable includes a dielectric element assembly including a plurality of dielectric layers laminated on each other in a direction of lamination, and a linear signal line provided in the dielectric element assembly. The dielectric element assembly includes at least one section bent in a plurality of places defining a zigzag shape when viewed in a plan view in the direction of lamination. In the zigzag section of the dielectric element assembly, any portions of the dielectric element assembly that are not adjacent across a bending line do not overlap when viewed in a plan view in the direction of lamination.

Abstract translation: 扁平电缆包括电介质元件组件，其包括在层叠方向上彼此层叠的多个电介质层和设置在电介质元件组件中的线性信号线。 电介质元件组件包括至少一个在层叠方向的俯视图中观察时在多个位置弯曲的部分，其限定Z字形。 在电介质元件组件的锯齿形部分中，当在俯视方向上的平面图中观察时，电介质元件组件中不邻近弯曲线的任何部分不重叠。

公开(公告)号：US08850700B2

公开(公告)日：2014-10-07

申请号：US12128238

申请日：2008-05-28

Applicant: Takayuki Sumida

Inventor： Takayuki Sumida

IPC: H05K3/02 ,  H05K1/16 ,  H05K3/24 ,  H05K7/06 ,  H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/12

CPC classification number: H05K3/245 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/16 ,  H05K3/06 ,  H05K3/12 ,  H05K7/06 ,  H05K2201/0391 ,  H05K2201/0969 ,  H05K2201/2072 ,  H05K2203/0108 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  H01L2924/00

Abstract: A wiring board includes a substrate having an adhesive surface, a first wiring, and a second wiring. The adhesive surface is in contact with the first wiring and the second wiring. The first wiring has a penetrating hole extending in a direction perpendicular to the adhesive surface. The second wiring has a first region, a second region, and a third region, which are adjacent regions arranged in that order. The first region is inside the penetrating hole in the first wiring and in contact with a first portion of the adhesive surface that forms part of the penetrating hole. The second region is in contact with the first wiring and faces the first wiring and the substrate. The third region is in contact with a second portion of the adhesive surface outside the first portion.

Abstract translation: 布线基板包括具有粘合表面的基板，第一布线和第二布线。 粘合剂表面与第一布线和第二布线接触。 第一布线具有沿垂直于粘合剂表面的方向延伸的穿透孔。 第二布线具有第一区域，第二区域和第三区域，它们是依次布置的相邻区域。 第一区域在第一布线中的穿透孔的内部，并与形成穿透孔的一部分的粘合剂表面的第一部分接触。 第二区域与第一布线接触并面向第一布线和基板。 第三区域与第一部分外部的粘合剂表面的第二部分接触。

公开(公告)号：US08839513B2

公开(公告)日：2014-09-23

申请号：US13963463

申请日：2013-08-09

Applicant: Hitachi Chemical Company, Ltd.

Inventor： Hidehiro Nakamura

IPC: H05K13/00

CPC classification number: H05K13/00 ,  G01D1/00 ,  G01D15/00 ,  H05K1/028 ,  H05K1/118 ,  H05K3/3447 ,  H05K3/365 ,  H05K3/4602 ,  H05K3/4635 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/09127 ,  H05K2201/09163 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/10151 ,  H05K2201/10189 ,  H05K2201/10598 ,  H05K2203/061 ,  H05K2203/167

Abstract: A method of manufacturing a concave connector substrate includes: a step of preparing a guide substrate having a guide/holding region that guides a plate-shaped connector to a connection position and a cut portion; a step of arranging and aligning two wiring substrates, each having wiring lines and through hole connection portions that are electrically connected to the wiring lines, with both surfaces of the guide substrate, and applying an adhesive to a predetermined region of the guide substrate to bond the wiring substrates to the guide substrate; a step of bending a portion of the wiring substrate toward the inside of the cut portion of the guide substrate and bringing the wiring lines disposed in the bent portion into pressure contact with the inside of the cut portion; and a step of removing a section inside the cut portion to form the guide/holding region.

Abstract translation: 一种制造凹形连接器基板的方法包括：准备具有将板状连接器引导到连接位置和切割部分的引导/保持区域的引导基板的步骤; 在导向基板的两个表面上布置和对准两个布线基板，每个布线基板具有布线和与布线电连接的通孔连接部分，并且将粘合剂施加到引导基板的预定区域以键合 布线基板到引导基板; 将布线基板的一部分朝向引导基板的切断部的内侧弯曲并使配置在弯曲部的布线与切断部的内部压力接触的步骤; 以及去除切割部分内的部分以形成引导/保持区域的步骤。

公开(公告)号：US20140268574A1

公开(公告)日：2014-09-18

申请号：US14290173

申请日：2014-05-29

Applicant: FUJIKURA LTD.

Inventor： Kazuhisa Itoi ,  Masahiro Okamoto

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K3/10 ,  H01L21/4857 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/08237 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11416 ,  H01L2224/11418 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/1336 ,  H01L2224/1339 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/73201 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80903 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8185 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8349 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15153 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/186 ,  H05K3/0061 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/0969 ,  H05K2201/10674 ,  Y10T29/49126 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/069 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2224/32 ,  H01L2924/00

Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.

Abstract translation: 一种组件内置板，其中堆叠有多个印刷布线基底，其具有形成在其树脂基底上的布线图案和通孔，并且包括内置于其中的电子部件，其中多个印刷的至少一部分 布线基底包括布线图案中的热布线，并且在通孔中包括热通孔，多个印刷布线基底中的至少一个在其中形成有电子部件构建的开口，并且在其中形成有导热层 并且紧贴在与内置于开口部的电子部件的电极形成面相反一侧的面上，电子部件通过形成有孔的层叠在导热层上的粘接层固定在开口部 在面向导热层的开口的区域中。

公开(公告)号：US20140232488A1

公开(公告)日：2014-08-21

申请号：US14262989

申请日：2014-04-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO

IPC: H01P3/08

CPC classification number: H01P3/08 ,  H01P3/085 ,  H05K1/0221 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/028 ,  H05K2201/055 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A flat cable includes a dielectric element assembly including a plurality of dielectric layers laminated on each other, a linear signal line provided in the dielectric element assembly, a first ground conductor provided on one side in a direction of lamination relative to the signal line and including a plurality of first openings arranged along the signal line, and a second ground conductor provided on the other side in the direction of lamination relative to the signal line and including a plurality of second openings arranged along the signal line. The first ground conductor is more distant from the signal line in the direction of lamination than is the second ground conductor. The first openings are larger than the second openings.

Abstract translation: 扁平电缆包括介质元件组件，其包括彼此层叠的多个电介质层，设置在电介质元件组件中的线性信号线，设置在相对于信号线的层叠方向的一侧上的第一接地导体， 沿着信号线布置的多个第一开口以及设置在相对于信号线的层叠方向的另一侧的第二接地导体，并且包括沿信号线布置的多个第二开口。 第一接地导体在层叠方向比信号线远离第二接地导体。 第一开口大于第二开口。

公开(公告)号：US20140202750A1

公开(公告)日：2014-07-24

申请号：US14148979

申请日：2014-01-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takeshi KOGURE ,  Hiromichi KITAJIMA

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/165 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/0969

Abstract: A multilayer substrate module includes a multilayer circuit substrate, a mounting land, and an input/output terminal. Inside the multilayer circuit substrate, a wiring line that connects the mounting land and the input/output terminal to each other, an inductor that defines a portion of the wiring line, a first ground conductor that is positioned on the one main surface side of the inductor, and a second ground conductor that is positioned on the other main surface side of the inductor are defined by conductor patterns. The area where inductor is located is not superposed with the area where the second ground conductor is located, when the one main surface or the other main surface of the multilayer circuit substrate is viewed in plan, the second ground conductor being closer to the layer where the inductor is located than the first ground conductor is.

Abstract translation: 多层基板模块包括多层电路基板，安装台面和输入/输出端子。 在多层电路基板的内部，将安装台面和输入输出端子彼此连接的布线，限定布线的一部分的电感器，位于第一接地导体的一个主面侧的第一接地导体 电感器和位于电感器的另一主表面侧的第二接地导体由导体图案限定。 电感器所在的区域不与第二接地导体所在的区域重叠，当在平面图中观察多层电路衬底的一个主表面或另一个主表面时，第二接地导体更靠近层 电感器位于第一接地导体之上。

公开(公告)号：US20140174808A1

公开(公告)日：2014-06-26

申请号：US13727439

申请日：2012-12-26

Applicant: Zhichao Zhang ,  Tao Wu ,  Gaurav Chawla ,  Jeffrey Lee

Inventor： Zhichao Zhang ,  Tao Wu ,  Gaurav Chawla ,  Jeffrey Lee

IPC: H05K1/11 ,  H05K13/00

CPC classification number: H05K1/113 ,  H05K1/0243 ,  H05K1/025 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09881 ,  H05K2201/10719

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.

Abstract translation: 公开了一种具有减小的电容的平面栅格阵列（LGA）焊盘。 通过衬垫的导电部分的厚度，通过一个或多个不导电的空隙来减小与衬底内的平行接地面重叠的焊盘的导电部分。 空隙可以允许由焊盘的周边限定的焊盘的接触面积保持相同，同时减少与平行接地平面重叠的导电部分。 焊盘和平行接地面之间的电容减少了与重叠导电面积减小成正比的量。

公开(公告)号：US08726495B2

公开(公告)日：2014-05-20

申请号：US12140042

申请日：2008-06-16

Applicant: Osamu Nakao ,  Reiji Higuchi ,  Syouji Ito ,  Masahiro Okamoto

Inventor： Osamu Nakao ,  Reiji Higuchi ,  Syouji Ito ,  Masahiro Okamoto

IPC: H05K3/20

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0397 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A base material (20) is arranged on top of at least one first internal layer base material (10), and a second internal base material (30) is arranged underneath the base material (10). And thereafter a surface layer circuitry conductive foil (40) is arranged underneath the base material (30), and subsequently these materials are colaminated for forming a colaminated body (80). While this colaminating operation, conductive portions being formed in the base materials 10, 30 are aligned to electrically connect one another for forming an internal circuitry. And thereafter, an interlayer conductive portion (51) being electrically connected to the internal circuitry is formed, and a minute circuitry is formed on the top of the base material (20) and the conductive foil (40) accordingly.

Abstract translation: 基材（20）布置在至少一个第一内层基材（10）的顶部上，并且第二内基材（30）布置在基材（10）的下方。 此后，表面层电路导电箔（40）布置在基底材料（30）的下面，随后将这些材料进行混合以形成一个混合体（80）。 在这种分层操作中，形成在基材10,30中的导电部分被对齐以彼此电连接以形成内部电路。 此后，形成电连接到内部电路的层间导电部分（51），并且相应地在基底材料（20）的顶部和导电箔（40）上形成分电路。