公开(公告)号：US09967982B2

公开(公告)日：2018-05-08

申请号：US13866835

申请日：2013-04-19

Applicant: Palo Alto Research Center Incorporated

Inventor： Eugene M. Chow

IPC: H05K3/32 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  G01R1/067

CPC classification number: H05K3/32 ,  G01R1/06727 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L24/73 ,  H01L2221/68331 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/1161 ,  H01L2224/1182 ,  H01L2224/1191 ,  H01L2224/13008 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/1355 ,  H01L2224/13564 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/819 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/281 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/10378 ,  Y10T29/49124 ,  Y10T29/49147 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099

Abstract: An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.

公开(公告)号：US20180122733A1

公开(公告)日：2018-05-03

申请号：US15853926

申请日：2017-12-25

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua CHEN ,  Cheng-Ta KO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/096 ,  H05K2201/10378

Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.

公开(公告)号：US09961769B2

公开(公告)日：2018-05-01

申请号：US14162002

申请日：2014-01-23

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

IPC: H05K1/11 ,  H01L23/498 ,  H01L23/00 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/12042 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10378 ,  H01L2924/014 ,  H01L2924/00

Abstract: The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.

公开(公告)号：US20180116056A1

公开(公告)日：2018-04-26

申请号：US15849624

申请日：2017-12-20

Applicant: Unimicron Technology Corp.

Inventor： Yin-Ju CHEN ,  Ming-Hao WU ,  Cheng-Po YU

IPC: H05K3/46 ,  H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H01L35/30 ,  H05K1/02 ,  H05K3/36 ,  G06F1/20 ,  H05K1/14 ,  H05K1/11

CPC classification number: H05K3/4647 ,  G06F1/206 ,  H01L23/12 ,  H01L23/13 ,  H01L23/4275 ,  H01L23/49827 ,  H01L35/30 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/14 ,  H05K1/181 ,  H05K1/185 ,  H05K1/187 ,  H05K3/36 ,  H05K3/4697 ,  H05K2201/048 ,  H05K2201/10219 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734

Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

公开(公告)号：US20180116050A1

公开(公告)日：2018-04-26

申请号：US15334734

申请日：2016-10-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Robert WENZEL ,  Tingdong Zhou ,  David Clegg

IPC: H05K1/11 ,  H05K3/34 ,  H05K1/14 ,  H05K1/02 ,  H05K1/09

CPC classification number: H05K1/115 ,  H05K1/0224 ,  H05K1/09 ,  H05K1/111 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/041 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/041

Abstract: Embodiments of an interconnect structure are provided, the interconnect structure including: a reference plane structure having a first major surface and a second major surface opposite the first major surface, the reference plane structure including a plurality of through holes from the first major surface to the second major surface; a plurality of conductive columns, each conductive column centered within a through hole; and a plurality of isolation structures, each isolation structure fills an annular region within the through hole between each conductive column and surrounding portion of the reference plane structure.

公开(公告)号：US20180098420A1

公开(公告)日：2018-04-05

申请号：US15549107

申请日：2015-08-20

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Kenichi KUBOYAMA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/0248 ,  H01L23/32 ,  H01L25/04 ,  H01L25/18 ,  H01L2224/16225 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/119 ,  H05K1/141 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K1/182 ,  H05K3/4046 ,  H05K7/02 ,  H05K2201/09218 ,  H05K2201/10378

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

公开(公告)号：US20180087767A1

公开(公告)日：2018-03-29

申请号：US15613073

申请日：2017-06-02

Applicant: Apple Inc.

Inventor： Glenn K. Trainer ,  Rong Liu ,  Benjamin A. Cousins ,  Yupin Sun ,  Jun Qi ,  Jason W. Brinsfield ,  Ethan L. Huwe ,  Craig M. Stanley ,  Molly J. Anderson ,  Javier Mendez

IPC: F21V33/00 ,  F21V5/00 ,  F21V3/00 ,  F21V23/04 ,  H04R1/02 ,  G06F3/16 ,  H04R1/40 ,  H04R3/12

CPC classification number: H04R1/2888 ,  F21V3/00 ,  F21V5/007 ,  F21V23/0485 ,  F21V33/0056 ,  G06F3/01 ,  G06F3/016 ,  G06F3/0202 ,  G06F3/03547 ,  G06F3/041 ,  G06F3/044 ,  G06F3/165 ,  H01H13/023 ,  H03K17/962 ,  H03K2217/960785 ,  H04R1/025 ,  H04R1/026 ,  H04R1/26 ,  H04R1/2811 ,  H04R1/2826 ,  H04R1/30 ,  H04R1/403 ,  H04R3/00 ,  H04R3/12 ,  H04R5/02 ,  H04R7/12 ,  H04R7/127 ,  H04R7/18 ,  H04R9/022 ,  H04R9/025 ,  H04R9/06 ,  H04R31/006 ,  H04R2201/028 ,  H04R2201/34 ,  H04R2201/401 ,  H04R2400/03 ,  H04R2400/13 ,  H04R2420/07 ,  H05K1/0274 ,  H05K1/141 ,  H05K2201/09063 ,  H05K2201/10106 ,  H05K2201/10378

Abstract: This disclosure relates to speakers and more specifically to an array speaker for distributing music uniformly across a room. A number of audio drivers can be radially distributed within a speaker housing so that an output of the drivers is distributed evenly throughout the room. In some embodiments, the exit geometry of the audio drivers can be configured to bounce off a surface supporting the array speaker to improve the distribution of music throughout the room. The array speaker can include a number of vibration isolation elements distributed within a housing of the array speaker. The vibration isolation elements can be configured reduce the strength of forces generated by a subwoofer of the array speaker.

公开(公告)号：US20180041026A1

公开(公告)日：2018-02-08

申请号：US15725572

申请日：2017-10-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： HIROKI SAKAMOTO

IPC: H02H7/16 ,  H05K1/18 ,  H01G4/002 ,  H05K3/46 ,  H01G4/258 ,  H05K3/40 ,  H05K3/34 ,  H05K1/11 ,  H01G4/40

CPC classification number: H02H7/16 ,  H01G2/06 ,  H01G4/002 ,  H01G4/248 ,  H01G4/258 ,  H01G4/30 ,  H01G4/40 ,  H05K1/0257 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/141 ,  H05K1/167 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/027 ,  H05K3/1233 ,  H05K3/341 ,  H05K3/3442 ,  H05K3/4053 ,  H05K3/4611 ,  H05K2201/0792 ,  H05K2201/09072 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2201/10181 ,  H05K2201/10378 ,  H05K2201/10553 ,  H05K2201/10636 ,  H05K2203/043 ,  H05K2203/046 ,  H05K2203/107

Abstract: An electronic-device having an intermediate connection layer interposed between a wiring substrate and an electronic component. The intermediate connection layer has a laminated structure including a rigid substrate and a flexible substrate. A first conductor part is formed on one principal surface of the flexible substrate, and second and third conductor parts are formed on both principal surfaces of the rigid substrate, respectively. The rigid substrate includes an opening, and the first conductor part of the flexible substrate includes a narrowed fuse part at a position opposite the opening. Windows are formed near the fuse part. The flexible substrate and the rigid substrate are electrically connected with each other via solder.

公开(公告)号：US20180026014A1

公开(公告)日：2018-01-25

申请号：US15722758

申请日：2017-10-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L25/065 ,  H01L23/00 ,  H05K1/11 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0271 ,  H05K1/11 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10613 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

公开(公告)号：US20180019198A1

公开(公告)日：2018-01-18

申请号：US15541080

申请日：2015-12-16

Applicant: SONY CORPORATION

Inventor： JUNICHI SATO

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/14 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2201/2009

Abstract: To achieve an interposer being capable of corresponding to a variety of pitch conversions and being inexpensive as compared to the one in the related art. An interposer including a resin lamination including connection terminals for a main board on one surface, and a glass sheet that is fixed along another surface of the resin lamination, the glass sheet having an exposed portion exposed from the resin lamination, the exposed portion being at least a part of a surface not facing to the resin lamination, the glass sheet including connection terminals for a semiconductor device on a surface of the exposed portion, and wiring being formed on a surface of the exposed portion to interconnect the connection terminals with an edge of the exposed portion.