公开(公告)号：US20240161815A1

公开(公告)日：2024-05-16

申请号：US18055047

申请日：2022-11-14

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Jason Golbus ,  Jesse San-Jey Wang

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4094

Abstract: Multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.

公开(公告)号：US11967396B2

公开(公告)日：2024-04-23

申请号：US17730401

申请日：2022-04-27

Applicant: NVIDIA Corp.

Inventor： Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Jaewon Lee

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1066 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/14

Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

公开(公告)号：US11966835B2

公开(公告)日：2024-04-23

申请号：US15929093

申请日：2019-01-23

Applicant: NVIDIA Corp.

Inventor： Ching-En Lee ,  Yakun Shao ,  Angshuman Parashar ,  Joel Emer ,  Stephen W. Keckler

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: A sparse convolutional neural network accelerator system that dynamically and efficiently identifies fine-grained parallelism in sparse convolution operations. The system determines matching pairs of non-zero input activations and weights from the compacted input activation and weight arrays utilizing a scalable, dynamic parallelism discovery unit (PDU) that performs a parallel search on the input activation array and the weight array to identify reducible input activation and weight pairs.

公开(公告)号：US11966348B2

公开(公告)日：2024-04-23

申请号：US15929094

申请日：2019-01-28

Applicant: NVIDIA Corp.

Inventor： Donghyuk Lee ,  James Michael O'Connor

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4009 ,  G06F13/4045 ,  G06F13/4282

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

公开(公告)号：US11936507B2

公开(公告)日：2024-03-19

申请号：US18182245

申请日：2023-03-10

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  John Poulton

IPC: H04L25/34 ,  H04B1/00 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04B1/0082

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

公开(公告)号：US11934867B2

公开(公告)日：2024-03-19

申请号：US17184420

申请日：2021-02-24

Applicant: NVIDIA Corp.

Inventor： Sana Damani ,  Mark Stephenson ,  Ram Rangan ,  Daniel Robert Johnson ,  Rishkul Kulkarni

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/3009 ,  G06F9/522

Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

公开(公告)号：US20240030918A1

公开(公告)日：2024-01-25

申请号：US17932091

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US11854660B2

公开(公告)日：2023-12-26

申请号：US17556046

申请日：2021-12-20

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang

IPC: G11C7/12 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/063 ,  G11C7/22

Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.

公开(公告)号：US20230411365A1

公开(公告)日：2023-12-21

申请号：US18462259

申请日：2023-09-06

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L25/16 ,  H01L23/5386 ,  H05K1/181 ,  H01L2225/1094 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H01L2225/107 ,  H05K2201/10015

Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.

公开(公告)号：US20230363093A1

公开(公告)日：2023-11-09

申请号：US17737297

申请日：2022-05-05

Applicant: NVIDIA Corp.

Inventor： MingYi Yu ,  Greg Bodi ,  Ananta Attaluri

IPC: H05K1/18 ,  H05K1/02 ,  H05K7/20 ,  H05K3/30

CPC classification number: H05K1/181 ,  H05K1/0213 ,  H05K7/209 ,  H05K3/303 ,  H05K2201/10325

Abstract: A circuit system includes an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of side pins around a periphery of the cutout.