公开(公告)号：US20080052905A1

公开(公告)日：2008-03-06

申请号：US11896774

申请日：2007-09-05

Applicant: Ryoichi Watanabe ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Joon-Sung Kim ,  Seung-Chul Kim ,  Myung-San Kang

Inventor： Ryoichi Watanabe ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Joon-Sung Kim ,  Seung-Chul Kim ,  Myung-San Kang

IPC: H05K3/02

CPC classification number: H05K3/0017 ,  H05K3/0014 ,  H05K3/045 ,  H05K3/06 ,  H05K3/107 ,  H05K3/20 ,  H05K3/205 ,  H05K3/426 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/0361 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2203/0278 ,  H05K2203/0384 ,  H05K2203/0582 ,  H05K2203/1152 ,  H05K2203/1189 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of fabricating a printed circuit board is disclosed. A method of fabricating a printed circuit board that includes: stacking an insulation layer on at least one surface of a core layer, on which an inner circuit is formed, and forming an outer circuit pattern; burying the outer circuit pattern in the insulation layer; removing the outer circuit pattern to form minute grooves and curing the insulation layer; and forming an outer circuit by filling metal in the minute grooves, makes it possible to readily form high-resolution fine-line circuits, as well as to reduce fabrication costs and increase productivity.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在形成有内部电路的芯层的至少一个表面上堆叠绝缘层，并形成外部电路图案; 将外部电路图案埋在绝缘层中; 去除外部电路图案以形成微小凹槽并固化绝缘层; 通过在金属槽中填充金属而形成外部电路，能够容易地形成高分辨率的细线电路，并且能够降低制造成本并提高生产率。

公开(公告)号：US20070289128A1

公开(公告)日：2007-12-20

申请号：US11581589

申请日：2006-10-17

Applicant: Kenji Takano ,  Munekazu Shibata ,  Kazuya Arai ,  Junichi Kanai ,  Kaoru Sugimoto

Inventor： Kenji Takano ,  Munekazu Shibata ,  Kazuya Arai ,  Junichi Kanai ,  Kaoru Sugimoto

IPC: H05K3/36

CPC classification number: H05K3/20 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for producing a circuit board includes the steps of etching the third metal layer of a three-layer metal laminate into a predetermined interconnection pattern by photolithography; forming a laminate on the interconnection pattern by a buildup method, the laminate including interconnection patterns with insulating layers provided therebetween, the interconnection patterns being electrically connected to each other; separating a first metal layer from a supporting substrate to detach the laminate; removing the first metal layer of the three-layer metal laminate by etching using a second metal layer as a barrier layer; and removing the exposed second metal layer by etching.

Abstract translation: 制造电路板的方法包括以下步骤：通过光刻将三层金属层压体的第三金属层蚀刻成预定的互连图案; 通过积层法在所述互连图案上形成层压体，所述层压体包括布置在其间的绝缘层的互连图案，所述互连图案彼此电连接; 从支撑基板分离第一金属层以分离层压体; 通过使用第二金属层作为阻挡层进行蚀刻来去除三层金属层叠体的第一金属层; 并通过蚀刻去除暴露的第二金属层。

公开(公告)号：US06977346B2

公开(公告)日：2005-12-20

申请号：US10458448

申请日：2003-06-10

Applicant: Vivek A. Jairazbhoy ,  Andrew Z. Glovatsky

Inventor： Vivek A. Jairazbhoy ,  Andrew Z. Glovatsky

IPC: H01L23/367 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40 ,  H05K1/00

CPC classification number: H05K1/0203 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/0361 ,  H05K2201/064 ,  H05K2201/09063 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2201/10689 ,  H01L2924/00

Abstract: The present invention provides a circuit board including a first conductor layer forming a plurality of conductive circuit traces for interconnecting electronic components. The circuit board includes a substrate for supporting the first conductor layer and a pedestal formed from the substrate for supporting at least one of the plurality of electronic components. The pedestal provides a heat conduction path for conducting heat away from the at least one of the plurality of electronic components and a aperture in the substrate adjacent the pedestal for allowing a fluid to pass through the substrate.

Abstract translation: 本发明提供了一种电路板，包括形成用于互连电子部件的多个导电电路迹线的第一导体层。 电路板包括用于支撑第一导体层的基板和由基板形成的基座，用于支撑多个电子部件中的至少一个。 基座提供用于将热量远离多个电子部件中的至少一个的热传导路径和邻近基座的基板中的孔，以允许流体通过基板。

公开(公告)号：US20050153483A1

公开(公告)日：2005-07-14

申请号：US10510588

申请日：2003-04-10

Applicant: Roelf Groenhuis ,  Paul Dijkstra ,  Cornelis Schriks ,  Peter Van De Water

Inventor： Roelf Groenhuis ,  Paul Dijkstra ,  Cornelis Schriks ,  Peter Van De Water

IPC: H01L23/12 ,  A23G3/00 ,  A23G3/36 ,  A23G4/00 ,  A23G4/12 ,  A23L1/28 ,  A23L1/30 ,  A61K35/74 ,  A61K35/747 ,  A61P1/02 ,  C12N1/14 ,  C12R1/225 ,  H01L21/48 ,  H01L23/31 ,  H05K1/18 ,  H05K3/06 ,  H01L21/44 ,  H01L21/50

CPC classification number: H05K3/062 ,  A23G3/366 ,  A23G4/123 ,  A23L33/135 ,  A23Y2220/77 ,  A61K35/747 ,  C12R1/225 ,  H01L21/4828 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/0361 ,  H05K2203/0384 ,  H05K2203/1469 ,  H05K2203/1476 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operations the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract translation: 载体（30）包括第一蚀刻掩模（14），第一金属层（11），中间层（12），第二金属层（13）和第二蚀刻掩模（17）。 可以通过电化学电镀在一个步骤中提供第一和第二蚀刻掩模（14,17）。 在通过第一蚀刻掩模（14）对第一金属层（11）和中间层（12）进行了图案化之后，可以使用导电装置将电气元件（20）适当地附接到载体（30）。 在这种图形化操作中，进一步蚀刻中间层（12），以便在第一金属层（11）下方产生不规则的凹凸。 在提供封装（40）之后，第二金属层（13）通过第二蚀刻掩模（17）构图。 以这种方式，在组装过程中获得无可光刻步骤的可焊接装置（10）。

公开(公告)号：US06838623B2

公开(公告)日：2005-01-04

申请号：US10300049

申请日：2002-11-20

Applicant: Lawrence Kneisel ,  Mohan Paruchuri ,  Vivek Jairazboy ,  Vladimir Stoica

Inventor： Lawrence Kneisel ,  Mohan Paruchuri ,  Vivek Jairazboy ,  Vladimir Stoica

IPC: H05K3/38 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K3/4641 ,  H05K3/386 ,  H05K3/4038 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/0397 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2203/1438

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

公开(公告)号：US06730391B1

公开(公告)日：2004-05-04

申请号：US09744333

申请日：2001-02-27

Applicant: Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida

Inventor： Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida

IPC: B32B1500

CPC classification number: H05K3/062 ,  H05K3/20 ,  H05K3/44 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10S428/901 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/24917

Abstract: In the present invention, which produces a clad sheet for a multilayered printed circuit board capable of being economically manufactured and having excellent performance, a multilayered printed circuit board using thereof and a manufacturing method thereof, a multilayered printed circuit board is manufactured by forming clad sheet for a multilayered printed circuit board 34 by laminating copper foil 19, 24, 33 which are to be formed into conductor layer 10, 17, 18 and nickel plating 20, 21 which are to be etching-stopper layer and simultaneously press-bonding both, producing a base by selectively etching clad sheet for a multilayered printed circuit board 34, forming outer conductor layer 15, 16 on the surface of the base and simultaneously making patterning, and electrically connecting among conductor layer 10, 15, 16 by interposing columnar conductor 17, 18 formed by etching copper foil 19, 24, 33 and nickel plating 20, 21.

Abstract translation: 在本发明中，制造了能够经济地制造并具有优异性能的多层印刷电路板用复合板，使用该多层印刷电路板及其制造方法的多层印刷电路板是通过将多层印刷电路板 将要形成为导体层10,17,18和镍镀层20,21的铜箔19,24,33的多层印刷电路板34，其被作为蚀刻停止层并同时压接两者，制造基底 通过选择性地蚀刻用于多层印刷电路板34的包覆片，在基底的表面上形成外部导体层15,16，并且同时进行图案化，并且通过插入通过蚀刻铜形成的柱状导体17,18，导电层10,15,16之间的电连接 箔19,24,33和镀镍20,21。

公开(公告)号：US20040065717A1

公开(公告)日：2004-04-08

申请号：US10399530

申请日：2003-09-29

Inventor： Kinji Saijo ,  Kazuo Yoshida ,  Hiroaki Okamoto ,  Shinji Ohsawa

IPC: B23K031/02

CPC classification number: H05K3/025 ,  B23K20/04 ,  B32B15/01 ,  H05K3/062 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2203/0384 ,  H05K2203/068 ,  Y10T428/12 ,  Y10T428/12438 ,  Y10T428/12896 ,  Y10T428/12979

Abstract: An adhesive-free multilayered metal laminate having a given thickness which is obtained by bonding a metal sheet having a thin metal film on a surface thereof to a metal foil without using an adhesive; and a process for continuously producing the laminate. The process comprises the steps of; setting a metal sheet on a reel for metal sheet unwinding; setting a metal foil on a reel for metal foil unwinding; unwinding the metal sheet from the metal sheet-unwinding reel and activating a surface of the metal sheet to thereby form a first thin metal film on the metal sheet surface; unwinding the metal foil from the metal foil-unwinding reel and activating a surface of the metal foil to thereby form a second thin metal film on the metal foil surface; and press-bonding the activated surface of the first thin metal film to that of the second thin metal film so that the first thin metal film formed on the metal sheet is in contact with the second thin metal film formed on the metal foil.

Abstract translation: 具有给定厚度的无粘合剂的多层金属层压体，其通过在其表面上将不具有金属薄膜的金属薄片接合而不使用粘合剂而获得; 以及连续制造层压体的方法。 该方法包括以下步骤： 将金属板放在卷轴上用于金属板退绕; 在金属箔退绕卷轴上设置金属箔; 从金属板退绕卷轴退绕金属片并激活金属片的表面，从而在金属片表面上形成第一薄金属膜; 从金属箔退绕卷轴退绕金属箔并激活金属箔的表面，从而在金属箔表面上形成第二薄金属膜; 并且将第一薄金属膜的活化表面压接到第二薄金属膜的活化表面，使得形成在金属片上的第一薄金属膜与形成在金属箔上的第二薄金属膜接触。

公开(公告)号：US06717067B2

公开(公告)日：2004-04-06

申请号：US10198341

申请日：2002-07-18

Applicant: Zhong-You Shi ,  Delin Li ,  Richard McMillan

Inventor： Zhong-You Shi ,  Delin Li ,  Richard McMillan

IPC: H01R1204

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US20030226688A1

公开(公告)日：2003-12-11

申请号：US10458448

申请日：2003-06-10

Applicant: Visteon Global Technologies, Inc.

Inventor： Vivek A. Jairazbhoy ,  Andrew Z. Glovatsky

IPC: H05K007/20

CPC classification number: H05K1/0203 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0272 ,  H05K3/341 ,  H05K3/4007 ,  H05K2201/0361 ,  H05K2201/064 ,  H05K2201/09063 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2201/10689 ,  H01L2924/00

Abstract: The present invention provides a circuit board including a first conductor layer forming a plurality of conductive circuit traces for interconnecting electronic components. The circuit board includes a substrate for supporting the first conductor layer and a pedestal formed from the substrate for supporting at least one of the plurality of electronic components. The pedestal provides a heat conduction path for conducting heat away from the at least one of the plurality of electronic components and a aperture in the substrate adjacent the pedestal for allowing a fluid to pass through the substrate.

Abstract translation: 本发明提供了一种电路板，包括形成用于互连电子部件的多个导电电路迹线的第一导体层。 电路板包括用于支撑第一导体层的基板和由基板形成的基座，用于支撑多个电子部件中的至少一个。 基座提供用于将热量远离多个电子部件中的至少一个的热传导路径和邻近基座的基板中的孔，以允许流体通过基板。

公开(公告)号：US06584682B2

公开(公告)日：2003-07-01

申请号：US09812345

申请日：2001-03-20

Applicant: Robert Edward Belke ,  Thomas Bernd Krautheim ,  Vivek Amir Jairazbhoy ,  Delin Li

Inventor： Robert Edward Belke ,  Thomas Bernd Krautheim ,  Vivek Amir Jairazbhoy ,  Delin Li

IPC: H05K320

CPC classification number: H05K3/4038 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10 for making multi-layer electronic circuit boards 148, 248 having aperture 146, 246 which may be selectively connected to an electrical ground potential.

Abstract translation: 一种用于制造具有孔146,246的多层电子电路板148,248的方法10，其可选择性地连接到电接地电位。