公开(公告)号：US07845956B1

公开(公告)日：2010-12-07

申请号：US12454908

申请日：2009-05-26

Applicant: Thomas Baycura

Inventor： Thomas Baycura

IPC: H01R12/00

CPC classification number: H05K1/0286 ,  H05K1/141 ,  H05K1/142 ,  H05K1/147 ,  H05K3/305 ,  H05K3/361 ,  H05K2201/049 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09963 ,  H05K2201/10689 ,  H05K2203/0195 ,  H05K2203/167 ,  Y10T29/49144

Abstract: An apparatus and method of providing an electrical component interface is disclosed. For one embodiment, the electrical component interface includes an electrical component adapter. The electrical component adapter includes an electronic component solder pattern for receiving and allowing attachment of an electrical component. An adhesive backing is adjacent a surface of the electrical component adapter. The adhesive backing provides attachment of the electrical component adapter to a second surface.

公开(公告)号：US07833049B2

公开(公告)日：2010-11-16

申请号：US12542688

申请日：2009-08-17

Applicant: Chien-Chun Wang ,  Shao-Kai Chen ,  Chi-Fan Wu

Inventor： Chien-Chun Wang ,  Shao-Kai Chen ,  Chi-Fan Wu

IPC: H01R12/24

CPC classification number: H01R12/7076 ,  H01R12/61 ,  H01R12/62 ,  H01R13/6593 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/049 ,  H05K2201/10287 ,  H05K2201/10356 ,  H05K2201/10371

Abstract: An electrical connector comprises a circuit board and a first housing, wherein the circuit board has a butt portion and a lap portion, the butt portion is formed thereon with a plurality of first contacts, the lap portion is formed thereon with a plurality of second contacts, the first contacts and the second contacts are connected with each other, the second spacing between the adjacent second contacts is larger than the first spacing between the adjacent first contacts, and the first contacts are arranged to couple to a butt connector. The first housing is assembled on the circuit board and positioned above the lap portion.

Abstract translation: 电连接器包括电路板和第一壳体，其中所述电路板具有对接部分和搭接部分，所述对接部分形成有多个第一触点，所述搭接部分形成有多个第二触点 第一触点和第二触点彼此连接，相邻的第二触点之间的第二间隔大于相邻的第一触点之间的第一间隔，并且第一触点被布置成耦合到对接连接器。 第一壳体组装在电路板上并且位于搭接部分上方。

公开(公告)号：US20100248547A1

公开(公告)日：2010-09-30

申请号：US12663822

申请日：2008-06-10

Applicant: Tamim Peter Sidiki ,  Horst Roehm ,  Robert Muir Gemmel Izat ,  Rob P. Weber ,  Hans-Martin Ritter

Inventor： Tamim Peter Sidiki ,  Horst Roehm ,  Robert Muir Gemmel Izat ,  Rob P. Weber ,  Hans-Martin Ritter

IPC: H01R13/66 ,  H01R43/00

CPC classification number: H01R13/6485 ,  H01R13/6666 ,  H05K1/0259 ,  H05K1/141 ,  H05K1/18 ,  H05K2201/049 ,  H05K2201/10189 ,  H05K2201/10515 ,  Y10T29/49208

Abstract: The present invention relates to an electrical connector for a first IC, comprising a second IC (12) carrying ESD protection, the second IC (12) being integrated into the connector (8), which enhances the ESD protection and preserves the RF performance of such connector (8). The present invention further relates to a method for making an electrical connector (8) for a first IC, comprising this step of providing ESD protection to the first IC by integrating a second IC (12) carrying ESD-protection into the connector (8).

Abstract translation: 本发明涉及一种用于第一IC的电连接器，包括承载ESD保护的第二IC（12），第二IC（12）集成到连接器（8）中，这增强了ESD保护并保持了RF性能 这种连接器（8）。 本发明还涉及一种用于制造用于第一IC的电连接器（8）的方法，包括通过将携带ESD保护的第二IC（12）集成到连接器（8）中来向第一IC提供ESD保护的步骤， 。

公开(公告)号：US07796400B2

公开(公告)日：2010-09-14

申请号：US11485772

申请日：2006-07-13

Applicant: Kenneth J. Kledzik ,  Jason C. Engle

Inventor： Kenneth J. Kledzik ,  Jason C. Engle

IPC: H05K7/12

CPC classification number: H05K1/14 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/01078 ,  H01L2924/15331 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/144 ,  H05K1/183 ,  H05K3/3436 ,  H05K7/12 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09954 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract translation: 公开了允许在电路板上布置三维阵列半导体芯片的装置和方法。 公开了一种独特的芯片载体，其中任何IC芯片可以在电路板上定位在另一个上。 此外，载体允许在载体上并在其下测试IC芯片，而不必从系统中移除载体和芯片，即使它们是BGA或CSP型。 运营商包括暴露的测试点，以便现场测试。

公开(公告)号：US07759781B2

公开(公告)日：2010-07-20

申请号：US11552256

申请日：2006-10-24

Applicant: Hideto Furuyama ,  Hiroshi Hamasaki

Inventor： Hideto Furuyama ,  Hiroshi Hamasaki

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0268 ,  H05K1/141 ,  H05K7/023 ,  H05K2201/049 ,  H05K2201/10704 ,  H05K2201/10719 ,  H01L2924/00

Abstract: A LSI package encompasses: an interposer having board-connecting joints, which facilitate connection with a printed wiring board, and module-connecting terminals, part of the module-connecting terminals are assigned as interposer-site monitoring terminals; a signal processing LSI mounted on the interposer; and an I/F module having a plurality of interposer-connecting terminals, which are arranged to correspond to arrangement of the module-connecting terminals, and a transmission line to establish an external interconnection of signal, which is transmitted from the signal processing LSI, part of the interposer-connecting terminals are assigned as module-site monitoring terminals. The interposer-site and module-site monitoring terminals are configured to flow a monitoring current to confirm electric contact between the signal processing LSI and the I/F module.

Abstract translation: LSI封装包括：具有板连接接头的插入件，其便于与印刷线路板的连接，以及模块连接端子，部分模块连接端子被分配为插入器位置监视端子; 安装在所述插入器上的信号处理LSI; 以及具有多个插入器连接端子的I / F模块，其被配置为对应于模块连接端子的配置，以及传输线，用于建立从信号处理LSI发送的信号的外部互连， 插入器连接端子的一部分被分配为模块站点监视终端。 中介站点和模块现场监视终端被配置为流动监视电流以确认信号处理LSI和I / F模块之间的电接触。

公开(公告)号：US07748110B2

公开(公告)日：2010-07-06

申请号：US11826758

申请日：2007-07-18

Applicant: Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

Inventor： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

IPC: H05K3/36

CPC classification number: H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0218 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/145 ,  H05K1/182 ,  H05K3/20 ,  H05K3/3442 ,  H05K3/361 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/043 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/302 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.

Abstract translation: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板，其具有上表面，与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。

公开(公告)号：US07732903B2

公开(公告)日：2010-06-08

申请号：US11760182

申请日：2007-06-08

Applicant: Jae Sung Oh

Inventor： Jae Sung Oh

IPC: H01L23/02

CPC classification number: H05K1/147 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10159 ,  H05K2201/10537 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory module includes a module substrate and a plurality of package units mounted to the module substrate such that they partially overlap each other. Each package unit has at least one memory semiconductor package attached thereto. Each package unit includes a flexible substrate, which has outer terminals provided over a lower surface adjacent to one edge thereof to form electrical connections with the module substrate, and the memory semiconductor package attached to one surface or each of both upper and lower surfaces of the flexible substrate.

Abstract translation: 存储器模块包括模块基板和安装到模块基板的多个封装单元，使得它们部分地彼此重叠。 每个封装单元具有至少一个连接到其上的存储器半导体封装。 每个封装单元包括柔性基板，其具有设置在与其一个边缘相邻的下表面上的外部端子，以形成与模块基板的电连接，并且存储器半导体封装件附接到所述模块基板的一个表面或两个上表面和下表面中的每一个 柔性基材。

公开(公告)号：US20100084177A1

公开(公告)日：2010-04-08

申请号：US12530708

申请日：2008-05-21

Applicant: Susumu Kumakura

Inventor： Susumu Kumakura

IPC: H05K1/14 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/06 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09427 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613

Abstract: Provided is an electronic circuit device in which the bonding state of electrodes can be detected easily with high precision. The electronic circuit device has a stack structure in which a plurality of electronic circuit boards (1a, 1b, 100a, 100b, 100c) are stacked in three or more layers through ball electrodes (10a, 10b, 20a, 20b) bonded to electrode pads (30a, 30b, 40b, 50a, 60a), wherein the electrode pads are disposed such that transmission shaded images of a pair of the electrode pads provided between adjacent layers partially overlap each other and have a non-overlapping region in which the transmission shaded images of the pair of electrode pads are free from overlapping and such that the transmission shaded image of the non-overlapping region is at least partially free from overlapping with transmission shaded images of all the other electrode pads.

Abstract translation: 提供一种可以容易地高精度地检测电极的接合状态的电子电路装置。 电子电路装置具有堆叠结构，其中多个电子电路板（1a，1b，100a，100b，100c）通过与电极焊盘（10a，10b，20a，20b）接合的三个或更多个层叠 （30a，30b，40b，50a，60a），其中电极焊盘被设置成使得设置在相邻层之间的一对电极焊盘的透射阴影图像部分地彼此重叠，并且具有不重叠的区域， 一对电极焊盘的图像没有重叠，使得非重叠区域的透射阴影图像至少部分地不与所有其它电极焊盘的透射阴影图像重叠。

公开(公告)号：US07662664B2

公开(公告)日：2010-02-16

申请号：US11780786

申请日：2007-07-20

Applicant: Michael Bauer ,  Ludwig Heitzer ,  Jens Pohl ,  Peter Strobel ,  Christian Stuempfl

Inventor： Michael Bauer ,  Ludwig Heitzer ,  Jens Pohl ,  Peter Strobel ,  Christian Stuempfl

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H05K1/141 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8388 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/3512

Abstract: An electronic circuit in a package-on-package configuration includes: a lower subassembly with a first electronic element, a first wiring carrier, a first housing with a first redistribution layer and an arrangement of solder balls disposed on the first redistribution layer and an upper subassembly with a second electronic element mounted on the lower subassembly. A method for producing the electronic circuit in a package-on-package configuration includes: adhering an upper side of the first electronic element to an underside of the first redistribution layer via a radiation-crosslinking thermoplastic adhesive.

Abstract translation: 封装在封装构造中的电子电路包括：具有第一电子元件的下部子组件，第一布线载体，具有第一再分布层的第一壳体和布置在第一再分布层上的焊球布置，以及上部 子组件具有安装在下部子组件上的第二电子元件。 一种封装在封装结构中的电子电路的制造方法，其特征在于，包括：通过辐射交联热塑性粘合剂将第一电子元件的上侧粘接到第一再分布层的下侧。

公开(公告)号：US07649375B2

公开(公告)日：2010-01-19

申请号：US11474921

申请日：2006-06-26

Applicant: Arash Behziz ,  Roya Yaghmai

Inventor： Arash Behziz ,  Roya Yaghmai

IPC: G01R31/26 ,  G01R31/28

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K3/3421 ,  H05K3/4602 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09627 ,  H05K2201/10189 ,  Y10T29/49165

Abstract: In one embodiment, a laminated printed circuit board translator is provided. In some embodiments, the translator includes a receiving board adapted to receive a pin, the receiving board includes a plated via extending through the receiving board and has a hole for receiving a pin. An interface board laminated with the receiving board has a controlled depth via extending through it to contact a conductive trace. The conductive trace extends between the receiving board and the interface board to connect the plated via of the receiving board with the controlled depth via of the interface board. The controlled depth via is configured so that it is capable of being plated through a single sided drilled opening in the interface board. Some embodiments have a pad on the interface board connected to the controlled depth via.

Abstract translation: 在一个实施例中，提供了层压印刷电路板转换器。 在一些实施例中，翻译器包括适于接收销的接收板，接收板包括延伸穿过接收板的电镀通孔，并具有用于接收销的孔。 与接收板层压的接口板具有通过其延伸的受控深度以接触导电迹线。 导电迹线在接收板和接口板之间延伸，以将接收板的电镀通孔与接口板的受控深度通孔连接。 受控深度通孔被配置成能够通过接口板中的单面钻孔而进行电镀。 一些实施例在接口板上具有连接到受控深度通孔的垫。