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    Connection substrate
    52.
    发明授权
    Connection substrate 有权
    连接基板

    公开(公告)号：US09000388B2

    公开(公告)日：2015-04-07

    申请号：US13640395

    申请日：2011-01-27

    Applicant: Fumiyuki Tokura ,  Mitsutoshi Sugiya ,  Shigeru Suzuki ,  Takashi Tonbe

    Inventor： Fumiyuki Tokura ,  Mitsutoshi Sugiya ,  Shigeru Suzuki ,  Takashi Tonbe

    IPC: G01T1/20 ,  H01R13/02 ,  H01R13/46 ,  H01L27/146 ,  H05K1/02 ,  H05K1/11

    CPC classification number: G01T1/2018 ,  H01L27/14623 ,  H01L27/14634 ,  H01L27/14661 ,  H01L27/14663 ,  H05K1/0218 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/113 ,  H05K2201/09727 ,  H05K2201/10545 ,  H05K2201/10674

    Abstract: A connection substrate 13 includes a base material 130 formed by stacking a plurality of dielectric layers 130a to 130f and a plurality of through conductors 20 provided penetrating through the dielectric layers 130c to 130f adjacent to each other. A plurality of radiation shielding films 21a to 23a formed integrally with each of the plurality of through conductors 20 and separated from each other are provided at two or more interlayer parts in the dielectric layers 130c to 130f. A region PR1 of the radiation shielding film 21a (21b) formed integrally with one through conductor 20 in one interlayer part projected onto a virtual plane normal to a predetermined direction and a region of the radiation shielding film 22b or 22c (22c) formed integrally with another through conductor 20 in another interlayer part projected onto the virtual plane do not overlap each other. Accordingly, the readout circuits of an integrated circuit device can be protected from radiation, and an increase in parasitic capacitance can be suppressed.

    Abstract translation: 连接基板13包括通过堆叠多个电介质层130a至130f而形成的基底材料130和穿过彼此相邻的电介质层130c至130f设置的多个贯穿导体20。 在电介质层130c〜130f的两个以上的层间部分设置有与多个贯通导体20中的每一个一体地形成并彼此分离的多个辐射屏蔽膜21a至23a。 辐射屏蔽膜21a（21b）的区域PR1与一个中间部分中的一个贯通导体20一体地形成，该层间部分投射到垂直于预定方向的虚拟平面上，并且辐射屏蔽膜22b或22c（22c）的区域与 投影到虚拟平面上的另一层间部分中的另一贯穿导体20彼此不重叠。 因此，集成电路器件的读出电路可以被保护免受辐射，并且可以抑制寄生电容的增加。

    INSULATION CIRCUIT AND COMMUNICATION EQUIPMENT
    55.
    发明申请
    INSULATION CIRCUIT AND COMMUNICATION EQUIPMENT 有权
    绝缘电路和通信设备

    公开(公告)号：US20140368291A1

    公开(公告)日：2014-12-18

    申请号：US14374596

    申请日：2012-10-09

    Applicant: YOKOGAWA ELECTRIC CORPORATION

    Inventor： Satoshi Mochizuki ,  Makoto Takeuchi

    IPC: H05K1/02 ,  H01P5/00 ,  H05K1/11

    CPC classification number: H05K1/025 ,  H01P1/20 ,  H01P1/203 ,  H01P5/00 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/0253 ,  H05K1/115 ,  H05K2201/09727

    Abstract: Disclosed is an insulation circuit comprising: a first pattern formed on a first layer of a substrate, that receives high-frequency signals; a second pattern formed on this first layer next to the first pattern and that outputs the high-frequency signals received by the first pattern; a third pattern formed on a second layer different from the first layer of the substrate and connected with a signal ground, in such a way that the first and second patterns respectively overlap in plan view; and a fourth pattern formed on the second layer next to the third pattern and connected with a frame ground, in such a way that the first and second patterns respectively overlap in plan view.

    Abstract translation: 公开了一种绝缘电路，包括：形成在衬底的第一层上的第一图案，其接收高频信号; 在该第一层上形成的与第一图案相邻并且输出由第一图案接收的高频信号的第二图案; 第三图案形成在不同于衬底的第一层并且与信号接地连接的第二层上，使得第一和第二图案在平面图中分别重叠; 以及形成在第三图案上的第二层上并与框架接地连接的第四图案，使得第一图案和第二图案在平面图中分别重叠。

    ELECTRONIC ASSEMBLIES INCLUDING A SUBASSEMBLY FILM AND METHODS OF PRODUCING THE SAME
    56.
    发明申请
    ELECTRONIC ASSEMBLIES INCLUDING A SUBASSEMBLY FILM AND METHODS OF PRODUCING THE SAME 审中-公开
    包括底片的电子组件及其制造方法

    公开(公告)号：US20140335635A1

    公开(公告)日：2014-11-13

    申请号：US13891637

    申请日：2013-05-10

    Applicant: Sridharan Venk ,  Adam Scotch ,  David Hamby

    Inventor： Sridharan Venk ,  Adam Scotch ,  David Hamby

    IPC: H01L23/00 ,  H01L33/48

    CPC classification number: H01L24/80 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/62 ,  H01L2924/12041 ,  H01L2924/12042 ,  H05K1/141 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/284 ,  H05K3/305 ,  H05K3/368 ,  H05K3/4069 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/09281 ,  H05K2201/09727 ,  H05K2201/10106 ,  H01L2924/00

    Abstract: Described herein are electronic assemblies including a subassembly film and methods for making the same. In some embodiments, a first subassembly is formed by placing an electronic die at a die placement location on a subassembly film. A second subassembly may be formed by placing the first subassembly at a subassembly placement position on a base layer, such that electrical contacts/traces on the first film overlap with electrical contacts/traces at a subassembly connection point on the base layer. Placement of the die on the subassembly film may be performed with automatic placement machinery that has a placement accuracy that is greater than that required to place the first subassembly on the base layer. As a result, the costly and time consuming manual inspection of die placement may be avoided.

    Abstract translation: 这里描述的是包括子组件膜的电子组件及其制造方法。 在一些实施例中，通过将电子管芯放置在子组件膜上的管芯放置位置来形成第一子组件。 第二子组件可以通过将第一子组件放置在基底层上的子组件放置位置而形成，使得第一膜上的电接触/迹线与基底层上的子组件连接点处的电触点/迹线重叠。 可以使用具有大于将第一子组件放置在基层上所需的放置精度的自动放置机械来执行模具在子组件薄膜上的放置。 结果，可以避免成本高且耗时的针头放置的手动检查。

    Paddle Card With Improved Performance
    57.
    发明申请
    Paddle Card With Improved Performance 有权
    具有改进性能的桨卡

    公开(公告)号：US20140202751A1

    公开(公告)日：2014-07-24

    申请号：US13745352

    申请日：2013-01-18

    Applicant: Molex Incorporated

    Inventor： Mark Alan BUGG

    IPC: H01R4/02 ,  H05K1/02

    CPC classification number: H05K1/0216 ,  H01R9/032 ,  H01R12/57 ,  H01R12/62 ,  H01R12/775 ,  H01R13/6474 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/112 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/09218 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09727 ,  H05K2201/10356

    Abstract: A paddle card construction disclosed for use in connecting electronic devices together. The paddle card takes the form of a circuit board that has a plurality of conductive contact pads arranged thereon in pairs. The contact pads of each pair are spaced apart from each other to provide a pair of points to which cable wire free ends may be terminated, such as by soldering. The spacing of the pads apart from each other in effect reduces to amount of capacitance in the cable wire termination area on the circuit board, thereby reducing the impedance and insertion loss in that area at high frequencies. The contact pads of each pair may be further interconnected together by a thin, conductive trace that extends lengthwise between the contact pads.

    Abstract translation: 公开的用于将电子设备连接在一起的桨卡结构。 桨卡采取电路板的形式，其具有成对地布置在其上的多个导电接触垫。 每对的接触垫彼此间隔开以提供一对点，电缆线自由端可以通过焊接方式终止于该点。 彼此分开的焊盘的间隔实际上减少到电路板上的电缆线端接区域中的电容量，从而降低了在该区域的高频下的阻抗和插入损耗。 每对的接触垫可以通过在接触垫之间纵向延伸的薄导电迹线进一步互连在一起。

    Electronic control device including interrupt wire
    58.
    发明授权
    Electronic control device including interrupt wire 有权
    电子控制装置包括中断线

    公开(公告)号：US08773833B2

    公开(公告)日：2014-07-08

    申请号：US13362497

    申请日：2012-01-31

    Applicant: Toru Itabashi ,  Yuuki Mikami ,  Takahiko Furuta ,  Ryoichi Shiraishi ,  Hiroaki Nakamura ,  Shigeki Nishiyama

    Inventor： Toru Itabashi ,  Yuuki Mikami ,  Takahiko Furuta ,  Ryoichi Shiraishi ,  Hiroaki Nakamura ,  Shigeki Nishiyama

    IPC: H02H5/04

    CPC classification number: H01H37/32 ,  H01H37/64 ,  H01H69/022 ,  H01H85/046 ,  H05K1/0293 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09727 ,  H05K2201/10181

    Abstract: An electronic control device includes a substrate, a plurality of component-mounted wires disposed on the substrate, a plurality of electronic components mounted on the respective component-mounted wires, a common wire disposed on the substrate and coupled with each of the electronic components, an interrupt wire coupled between one of the component-mounted wires and the common wire, a connection wire via which the interrupt wire is coupled with one of the common wire and the one of the component-mounted wires, and a solder disposed between each of the electronic components and a corresponding one of the component-mounted wires and having a lower melting point than the interrupt wire. The interrupt wire is configured to melt in accordance with heat generated by an overcurrent so as to interrupt a coupling between the one of the component-mounted wires and the common wire.

    Abstract translation: 电子控制装置包括基板，设置在基板上的多个部件安装的线，安装在各个部件安装的导线上的多个电子部件，设置在基板上并与每个电子部件耦合的公共线， 连接在组件安装线中的一个和公共线之间的中断线，连接线，中断线通过该连接线与公共线中的一个和部件安装的线中的一个耦合，以及布置在每个之间的焊料 电子部件和相应的部件安装线中的一个并且具有比中断线更低的熔点。 中断线被配置为根据由过电流产生的热量熔化，以便中断一个部件安装的线和公共线之间的耦合。

    HIGH-FREQUENCY SIGNAL LINE AND ELECTRONIC DEVICE
    59.
    发明申请
    HIGH-FREQUENCY SIGNAL LINE AND ELECTRONIC DEVICE 有权
    高频信号线和电子设备

    公开(公告)号：US20140184360A1

    公开(公告)日：2014-07-03

    申请号：US14196301

    申请日：2014-03-04

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Noboru KATO

    IPC: H01P3/08

    CPC classification number: H01P3/082 ,  H01P3/08 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09618 ,  H05K2201/09727

    Abstract: A high-frequency signal line includes an element assembly including a plurality of insulator layers, a linear signal line provided in or on the element assembly, a first ground conductor provided in or on the element assembly and extending along the signal line, and a plurality of floating conductors provided in or on the element assembly on a first side in a direction of lamination relative to the signal line and the first ground conductor, so as to be arranged along the signal line in an orientation crossing the signal line when viewed in a plan view in the direction of lamination. The floating conductors are opposite to the signal line and the first ground conductor with at least one of the insulator layers positioned therebetween, the floating conductors being connected to neither the signal line nor the first ground conductor. A capacitance is created between the first ground conductor and each of the floating conductors, and has a greater value than a capacitance created between the signal line and the floating conductor.

    Abstract translation: 高频信号线包括元件组件，其包括多个绝缘体层，设置在元件组件中或其上的线性信号线，设置在元件组件中或其上并沿着信号线延伸的第一接地导体，以及多个 设置在所述元件组件中或所述元件组件上的相对于所述信号线和所述第一接地导体的层叠方向的第一侧上的浮动导体，以便沿着所述信号线以与所述信号线相交的方向布置在所述信号线上 在层叠方向的平面图。 浮动导体与信号线和第一接地导体相对，其中至少一个绝缘体层位于它们之间，浮动导体既不连接到信号线也不连接到第一接地导体。 在第一接地导体和每个浮动导体之间产生电容，并且具有比在信号线和浮动导体之间产生的电容更大的值。

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