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    Insulating circuit board and power semiconductor apparatus employing the same
    51.
    发明授权
    Insulating circuit board and power semiconductor apparatus employing the same 失效
    绝缘电路板和采用该绝缘电路板的功率半导体装置

    公开(公告)号：US06504110B1

    公开(公告)日：2003-01-07

    申请号：US09655488

    申请日：2000-09-05

    Applicant: Junpei Kusukawa ,  Ryozo Takeuchi

    Inventor： Junpei Kusukawa ,  Ryozo Takeuchi

    IPC: H01R909

    CPC classification number: H05K3/22 ,  H01L23/3735 ,  H01L2924/0002 ,  H05K1/0257 ,  H05K1/0306 ,  H05K3/244 ,  H05K3/38 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09145 ,  H05K2201/098 ,  H05K2203/0346 ,  H05K2203/105 ,  H05K2203/107 ,  H05K2203/128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

    Abstract: In order to restrict a local concentration of an electric field in a conductor layer end portion of an insulating circuit board and increase a partial electric discharge starting voltage, thereby improving an insulating reliability of the insulating circuit board and a power semiconductor apparatus employing the same, the present invention provides a method of manufacturing a insulating circuit board comprising the step of applying a voltage between the circuit patterns of the insulating circuit board in an atmospheric or depressurized gas so as to allow the circuit board to discharge electricity, or irradiating a laser beam, thereby a projection shape of the end portion of the electrode conductor is melted and smoothened so as to restrict the concentration of the electric field.

    Abstract translation: 为了限制绝缘电路板的导体层端部中的电场的局部浓度，并且增加了部分放电起始电压，从而提高了绝缘电路板和使用该绝缘电路板的功率半导体装置的绝缘可靠性， 本发明提供了一种制造绝缘电路板的方法，包括以下步骤：在绝缘电路板的电路图案之间在大气压或减压气体中施加电压，以允许电路板放电，或照射激光束 从而使电极导体的端部的突出形状熔化和平滑化，从而限制电场的浓度。

    Printed circuit assembly with flexible support
    53.
    发明授权
    Printed circuit assembly with flexible support 失效
    具有灵活支撑的印刷电路组件

    公开(公告)号：US06353188B1

    公开(公告)日：2002-03-05

    申请号：US09365668

    申请日：1999-08-02

    Applicant: Salvador Gomez Fernandez

    Inventor： Salvador Gomez Fernandez

    IPC: H05K100

    CPC classification number: H05K1/028 ,  H05K1/0265 ,  H05K3/386 ,  H05K2201/09263 ,  H05K2201/098

    Abstract: A circuit assembly having a plurality of tracks formed from a conductive material secured to a flexible substrate by an adhesive. The adhesive is selected to withstand high temperatures and strains caused by folding the flexible substrate.

    Abstract translation: 一种电路组件，其具有由导电材料形成的多个轨道，该导电材料通过粘合剂固定到柔性基底上。 选择粘合剂以承受通过折叠柔性基材引起的高温和应变。

    Semiconductor substrates of high reliability ceramic metal composites
    54.
    发明授权
    Semiconductor substrates of high reliability ceramic metal composites 失效
    高可靠性陶瓷金属复合材料的半导体衬底

    公开(公告)号：US6054762A

    公开(公告)日：2000-04-25

    申请号：US917327

    申请日：1997-08-25

    Applicant: Masami Sakuraba ,  Masami Kimura ,  Junji Nakamura ,  Masaya Takahara

    Inventor： Masami Sakuraba ,  Masami Kimura ,  Junji Nakamura ,  Masaya Takahara

    IPC: C04B37/02 ,  H01L23/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/373 ,  H05K1/02 ,  H05K1/03 ,  H05K3/38 ,  H01L23/06 ,  H01L23/10 ,  H01L23/34

    CPC classification number: H01L23/3735 ,  C04B37/026 ,  H01L23/13 ,  H01L23/15 ,  H05K1/0271 ,  C04B2237/124 ,  C04B2237/125 ,  C04B2237/127 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/407 ,  C04B2237/70 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0355 ,  H05K2201/09145 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K3/38

    Abstract: A paste of active metallic brazing material is applied to the entire surface of each side of aluminum nitride or alumina ceramic substrate 1; circuit forming copper plate 3 having a thickness of 0.3 mm is placed in contact with one surface of the substrate and a heat dissipating copper plate 4 having a thickness of 0.25 mm placed in contact with the other surface; the individual members are compressed together and heated at 850.degree. C. in a vacuum furnace to form a joint; an etching resist is applied to the circuit forming copper plate and etching is performed with an iron chloride solution to form a circuit pattern and the unwanted brazing material is removed from the marginal portions; a second resist layer is applied and etched with an iron chloride solution to form a second marginal step; a third resist layer is similarly applied and etched to form a third marginal step; the completed circuit board having three marginal steps of which the lowest one is solely or partly made of the brazing material can withstand 1,500 heat cycles, which is the result that has ben unattainable by the prior art. Having such high heat cycle characteristics, the circuit board is suitable for use as semiconductor substrate in automobiles, electric trains and other applications that require high output power.

    Abstract translation: 在氮化铝或氧化铝陶瓷基板1的各侧的整个表面上涂敷活性金属钎料的糊状物， 将厚度为0.3mm的电路形成铜板3放置成与基板的一个表面接触，并且将厚度为0.25mm的散热铜板4放置成与另一个表面接触; 将各个构件压缩在一起，并在真空炉中在850℃下加热以形成接头; 将抗蚀剂施加到形成铜电路的电路上，用氯化铁溶液进行蚀刻以形成电路图案，并且从边缘部分去除不想要的钎焊材料; 施加第二抗蚀剂层并用氯化铁溶液蚀刻以形成第二边缘步骤; 类似地施加和蚀刻第三抗蚀剂层以形成第三边缘步骤; 完成的电路板具有三个边缘台阶，其中最低的一个仅由或部分由钎焊材料制成，可承受1500次热循环，这是现有技术无法实现的结果。 具有这样高的热循环特性，电路板适用于需要高输出功率的汽车，电动列车和其他应用中的半导体衬底。

    Process to decrease the strength of an electric field produced by a high voltage conductive path of a printed circuit board and printed circuit assembly using same
    55.
    发明授权
    Process to decrease the strength of an electric field produced by a high voltage conductive path of a printed circuit board and printed circuit assembly using same 失效
    降低由印刷电路板上的高压导电路径产生的电场的强度和使用它的印刷电路组件的工艺

    公开(公告)号：US5814203A

    公开(公告)日：1998-09-29

    申请号：US563622

    申请日：1995-11-28

    Applicant: Pascal Gaston Raymond Delporte ,  Pierre Paul Roger Willy Depireux

    Inventor： Pascal Gaston Raymond Delporte ,  Pierre Paul Roger Willy Depireux

    IPC: H05K1/02 ,  H05K3/06 ,  H05K3/24 ,  H05K3/34 ,  C25D5/50

    CPC classification number: H05K3/3473 ,  H05K1/0257 ,  H05K1/0254 ,  H05K2201/09272 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/043 ,  H05K2203/0776 ,  H05K3/062 ,  H05K3/244 ,  H05K3/3494

    Abstract: A process to decrease the strength of an electric field produced by a high voltage conductive path on a printed circuit board and printed circuit assembly using same includes the steps of coating the upper side (5) of the conductive path or track (1) with a thick layer of electrically conductive coating material (4); and reflowing so that the upper edges (8, 9) of the track (1) are also covered with a relatively thick layer of coating material. The track (1) is thus embedded in a mass of coating material having more or less a rounded-shaped cross-section and the sharp upper edges (8, 9) of this track, where a strong electrical field is generally produced, are smoothed. As a result, the strength of the electrical field around the track (1) is reduced. In a preferred embodiment, a second track (13) similar to the first track (1) is created symmetrically thereto on the opposite surface (14) of the printed circuit board (3). This second track (13) is brought to the same potential as the first track (1) and is coated in a same way. Therefore, the electrical fields still produced at the lower edges (10, 11) of the track (1), which are not totally embedded in the mass of coating material because the latter do not adhere on the surface (2) of the printed circuit board (3), are counterbalanced by the electrical fields produced at corresponding opposite edges (15, 16) of the second track (13). The strength of the global electrical field around the tracks (1, 13) is thereby drastically reduced.

    Abstract translation: 降低由印刷电路板上的高压导电路径产生的电场的强度和使用它的印刷电路组件的工艺包括以下步骤：用导电路径或轨道（1）涂覆上侧（5） 厚层的导电涂层材料（4）; 并回流，使得轨道（1）的上边缘（8,9）也被相对厚的涂层材料覆盖。 轨道（1）因此被嵌入到具有或多或少具有圆形横截面的涂层材料块中，并且通常产生强电场的该轨道的锋利的上边缘（8,9）被平滑化 。 结果，轨道（1）周围的电场强度降低。 在优选实施例中，与印刷电路板（3）的相对表面（14）对称地形成类似于第一轨道（1）的第二轨道（13）。 该第二轨道（13）被带到与第一轨道（1）相同的电位并以相同的方式被涂覆。 因此，在轨道（1）的下边缘（10,11）处仍然产生的电场，由于后者不粘附在印刷电路的表面（2）上，所以不完全嵌入涂层材料中 板（3）由在第二轨道（13）的对应的相对边缘（15,16）处产生的电场平衡。 轨道（1,13）周围的全局电场的强度因此大大降低。

    IC card and mating socket
    57.
    发明授权
    IC card and mating socket 失效
    IC卡和配套插座

    公开(公告)号：US4909742A

    公开(公告)日：1990-03-20

    申请号：US296175

    申请日：1989-01-12

    Applicant: Isao Ohkubo ,  Shintaro Aiba

    Inventor： Isao Ohkubo ,  Shintaro Aiba

    IPC: B42D15/02 ,  B42D15/10 ,  G06K7/00 ,  G06K19/077 ,  H05K1/11 ,  H05K3/40

    CPC classification number: H05K1/117 ,  G06K19/07743 ,  G06K7/0047 ,  H05K2201/09154 ,  H05K2201/09645 ,  H05K2201/098 ,  H05K2203/0346 ,  H05K2203/1327 ,  H05K3/403

    Abstract: A credit card type small thin rectangular IC Card has a battery and an IC comprising a CPU, a ROM and a RAM mounted on a flexible printed circuit and bonded within an insulative plastic material. The printed circuit of the card has a plurality of electrode terminals exposed in a parallel array along at least one edge of the card which are adapted to engage contacts of a mating socket. The printed circuit terminals are manufactured by coating copper, nickel and gold over polyamide resin and squeeze finishing the leading edge. The mating socket comprises a general U-shaped frame having a U-shaped channel adapted to receive the IC card and having internal recessed contacts adapted to engage the terminals of the IC card. The contacts extend from an exterior surface of the frame for interconnection with the circuits of a mating device. Downwardly projecting portions thereof are bent at least twice in the portion penetrating the bottom of the frame.

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