公开(公告)号：US09532468B2

公开(公告)日：2016-12-27

申请号：US14549951

申请日：2014-11-21

Applicant: IBIDEN Co., Ltd.

Inventor： Masatoshi Kunieda ,  Makoto Terui ,  Ryoujiro Tominaga ,  Takashi Kariya

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/24 ,  H05K3/34

CPC classification number: H05K3/4682 ,  H01L2224/16227 ,  H05K1/0256 ,  H05K1/0265 ,  H05K1/09 ,  H05K1/112 ,  H05K1/113 ,  H05K1/114 ,  H05K1/185 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/0989 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/1394 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.

Abstract translation: 布线基板包括第一树脂绝缘层，第一绝缘层上包括第一和第二导体焊盘的导体焊盘，覆盖第一和第二焊盘的第一绝缘层上的第二树脂绝缘层，第二绝缘层上的最外层导体层 包括第一和第二最外面布线层，通过第二绝缘层的通孔导体包括连接第一布线层和第一焊盘的第一通孔导体和连接第二布线层和第二焊盘的第二通孔导体，以及在第二绝缘层上的阻焊层 绝缘层，使得阻焊层覆盖第一布线层并且具有暴露第二布线层的一个或多个开口。 第一布线层包括第一主金属，第二布线层包括与第一布线层的第一金属不同的第二主金属。

公开(公告)号：US20160358836A1

公开(公告)日：2016-12-08

申请号：US14732119

申请日：2015-06-05

Applicant: International Business Machines Corporation

Inventor： Evan G. Colgan ,  Yi Pan ,  Hilton T. Toy ,  Jeffrey A. Zitz

IPC: H01L23/367 ,  H05K3/30 ,  H01L21/52 ,  H01L23/04 ,  H01L23/498

CPC classification number: H01L21/52 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/00014 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16793 ,  H01L2924/171 ,  H01L2924/1715 ,  H01L2924/176 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/2018 ,  H01L2924/014

Abstract: An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat spreader may further be arranged orthogonal to the first directional heat spreader. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes an opening that accepts the IC chip and may be attached to the top surface of the carrier. The IC chip is concentrically arranged within the opening of the stiffening frame. The first directional heat spreader is attached to the stiffening frame and to the IC chip and generally removes heat in a first opposing bivector direction. When included in the IC chip module, the second directional heat spreader is attached to the stiffening frame and to the first directional heat spreader and generally removes heat in a second opposing bivector direction orthogonal to the first opposing bivector direction.

Abstract translation: 集成电路（IC）芯片模块包括载体，加强框架，IC芯片和第一定向散热器。 第二定向散热器还可以布置成与第一定向散热器正交。 载体具有构造成电连接到母板的顶表面和底表面。 加强框架包括容纳IC芯片并且可以附接到载体的顶表面的开口。 IC芯片同心地布置在加强框架的开口内。 第一定向散热器附接到加强框架和IC芯片，并且通常在第一相对的双向驱动器方向上移除热量。 当包括在IC芯片模块中时，第二定向散热器附接到加强框架和第一定向散热器，并且通常在与第一相对的双向驱动器方向正交的第二相对的双向驱动器方向上去除热量。

公开(公告)号：US20160351543A1

公开(公告)日：2016-12-01

申请号：US15117345

申请日：2015-01-28

Applicant: LG INNOTEK CO., LTD.

Inventor： Sung Wuk RYU ,  Dong Sun KIM ,  Ji Haeng LEE ,  Sang Hyuck NAM

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15701 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/144 ,  H05K1/186 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: A printed circuit board according to the present invention comprises: an insulating substrate; a plurality of pads formed on the upper surface of the insulating substrate; a protective layer which comprises an opening part for exposing the upper surfaces of the plurality of pads, and is formed on the insulating substrate; and a metal bump which is formed on the first pad and the second pad in the plurality of pads, and projects above the surface of the protective layer, and, here, the first pad is formed to the left of the central upper part of the insulating substrate, while the second pad is formed to the right of the central upper part of the insulating substrate.

Abstract translation: 根据本发明的印刷电路板包括：绝缘基板; 形成在所述绝缘基板的上表面上的多个焊盘; 保护层，其包括用于暴露所述多个焊盘的上表面的开口部，并且形成在所述绝缘基板上; 以及金属凸块，其形成在所述多个焊盘中的所述第一焊盘和所述第二焊盘上，并且在所述保护层的表面上方突出，并且在这里，所述第一焊盘形成在所述保护层的中央上部的左侧 绝缘基板，而第二焊盘形成在绝缘基板的中央上部的右侧。

公开(公告)号：US09497864B2

公开(公告)日：2016-11-15

申请号：US13898486

申请日：2013-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H05K3/28

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US20160322284A1

公开(公告)日：2016-11-03

申请号：US15205416

申请日：2016-07-08

Applicant: HARRIS CORPORATION

Inventor： MICHAEL RAYMOND WEATHERSPOON ,  DAVID B. NICOL ,  LOUIS JOSEPH RENDEK, JR.

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/4985 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1511 ,  H01L2924/1579 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K1/189 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4632 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0141 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49224 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Abstract translation: 一种用于制造电子器件的方法，包括在牺牲衬底上形成互连层堆叠并且具有多个图案化的导电层，以及在相邻的图案化电导体层之间的介电层。 该方法还包括通过液晶聚合物（LCP）衬底的金属间键合层叠和电连接到与牺牲衬底相对的一侧上的互连层堆叠。 该方法还包括去除牺牲衬底以暴露最下图案化电导体层，并将至少一个第一器件电耦合到最下图案化电导体层。

公开(公告)号：US20160309575A1

公开(公告)日：2016-10-20

申请号：US15198110

申请日：2016-06-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hong MIN ,  Myung Sam KANG ,  Jung Han LEE ,  Young Gwan KO

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0204 ,  H05K1/0207 ,  H05K1/0209 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10416 ,  H05K2201/10674 ,  H05K2201/10727

Abstract: A circuit board includes an insulating part including insulating layers, metal layers disposed on the insulating layers, vias each passing through at least one insulating layer among the insulating layers and connecting together at least two metal layers among the metal layers; a first thermally conductive structure including a thermally conductive material, at least a part of the thermally conductive structure being inserted into the insulating part, a first via having one surface contacting the first thermally conductive structure, a first metal pattern contacting another surface of the first via, a first bonding member connected to the first metal pattern, and pads to which a first electronic component is connected on an outermost surface of a metal layer disposed on an outermost surface of the insulating part, the pads being at least in a first region and a second region having a higher temperature than the first region.

Abstract translation: 电路板包括绝缘部分，其包括绝缘层，设置在绝缘层上的金属层，每个穿过绝缘层中的至少一个绝缘层的通孔，并将金属层中的至少两个金属层连接在一起; 包括导热材料的第一导热结构，所述导热结构的至少一部分插入到所述绝缘部分中，具有与所述第一导热结构接触的一个表面的第一通孔，第一金属图案与所述第一导热结构的第一 通孔，连接到第一金属图案的第一接合构件以及在布置在绝缘部分的最外表面上的金属层的最外表面上连接有第一电子部件的焊盘，所述焊盘至少在第一区域中 以及具有比第一区域更高的温度的第二区域。

公开(公告)号：US20160284637A1

公开(公告)日：2016-09-29

申请号：US15172029

申请日：2016-06-02

Applicant: Qing Ma ,  Quan A. Tran ,  Robert L. Sankman ,  Johanna M. Swan ,  Valluri R. Rao

Inventor： Qing Ma ,  Quan A. Tran ,  Robert L. Sankman ,  Johanna M. Swan ,  Valluri R. Rao

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/15

CPC classification number: H05K1/112 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/15 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K3/0014 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10287 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0228 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的玻璃芯基板的实施例。 玻璃芯基板包括在玻璃芯的相对侧上的玻璃芯和堆积结构。 导电端子可以形成在玻璃芯基板的两侧。 IC芯片可以与衬底的一侧上的端子耦合，而相对侧上的端子可以与诸如电路板的下一级组件耦合。 玻璃芯可以包括其中已经形成导体的单片玻璃，或者玻璃芯可以包括已经连接在一起的两个或更多个玻璃部分，每个部分具有导体。 导体延伸穿过玻璃芯，并且一个或多个导体可以与设置在玻璃芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：US09426898B2

公开(公告)日：2016-08-23

申请号：US14750186

申请日：2015-06-25

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Guy Frick ,  Thomas J. Colosimo, Jr. ,  Horst Clauberg

IPC: B23K31/02 ,  H05K3/34 ,  B23K1/00 ,  B23K1/20 ,  B23K3/04 ,  B23K3/08

CPC classification number: H05K3/34 ,  B23K1/0016 ,  B23K1/203 ,  B23K3/04 ,  B23K3/082 ,  B23K2101/42 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/75161 ,  H01L2224/75184 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81204 ,  H05K3/3489 ,  H05K3/3494 ,  H05K2201/10674 ,  H05K2203/04 ,  H01L2924/014

Abstract: A thermocompression bonder is provided. The thermocompression bonder includes: a bond head including a heated bonding tool for bonding a semiconductor element to a substrate; and a flux application tool for applying a flux material to conductive contacts of the substrate prior to bonding of the semiconductor element to the substrate.

Abstract translation: 提供热压接机。 热压接机包括：接合头，其包括用于将半导体元件接合到衬底的加热焊接工具; 以及焊剂施加工具，用于在将半导体元件接合到衬底之前将焊剂材料施加到衬底的导电触点。

公开(公告)号：US09420687B2

公开(公告)日：2016-08-16

申请号：US14483934

申请日：2014-09-11

Applicant: HARRIS CORPORATION

Inventor： Michael Raymond Weatherspoon ,  David B. Nicol ,  Louis Joseph Rendek, Jr.

IPC: H05K5/00 ,  H05K1/03 ,  H01L21/683 ,  H01L25/065 ,  H05K1/18 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40 ,  H05K3/34 ,  H05K3/46 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1511 ,  H01L2924/1579 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K1/189 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4632 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0141 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49224 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Abstract translation: 一种用于制造电子器件的方法，包括在牺牲衬底上形成互连层堆叠并且具有多个图案化的导电层，以及在相邻的图案化电导体层之间的介电层。 该方法还包括通过液晶聚合物（LCP）衬底的金属间键合层叠和电连接到与牺牲衬底相对的一侧上的互连层堆叠。 该方法还包括去除牺牲衬底以暴露最下图案化电导体层，并将至少一个第一器件电耦合到最下图案化电导体层。

公开(公告)号：US09418928B2

公开(公告)日：2016-08-16

申请号：US14453858

申请日：2014-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/40 ,  H01L23/00 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16157 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Abstract translation: 实施例装置包括电介质层，电介质层中的导电迹线和凸块焊盘。 导电迹线包括具有暴露的顶表面的第一部分，其中暴露的顶表面从电介质层的顶表面凹陷。 此外，凸块焊盘设置在导电迹线的第二部分上并与其电连接。